Hardware Design Engineer - Graphics Silicon Implementation

Qualcomm; San Diego (CA); On-site; USD 161,800 - 242,600; Full time

Benefits offered by this job

Competitive annual discretionary bonus program

Opportunities for annual RSU grants

Job summary

Qualcomm is seeking an Engineer for its Adreno GPU team in San Diego, California. The role involves integrating and implementing GPU cores, working closely with architecture and design teams to ensure quality and performance. The candidate should have a strong understanding of RTL design and ASIC design flow.

With a competitive salary range of $161,800 to $242,600, Qualcomm offers a comprehensive benefits package designed to support employees' work-life balance and success.

Qualifications

• 0-5 years relevant industry experience.
• Understanding of digital design and RTL development.
• Basic knowledge of synthesis and formal verification.

Responsibilities

• Integrate, implement, and develop GPU cores.
• Collaborate with architecture and design teams.
• Manage design goals in power, performance, and area.

Skills

Verilog and System-Verilog languages

RTL integration

Synthesis understanding

Static timing analysis

Collaborative skills

Education

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field

Tools

Synopsys Design Compiler tools

Formal Verification tools

Job description

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > GPU ASICS Engineering

General Summary

Qualcomm CDMA Technologies, is the world leader in wireless ICs powering the majority of 3G & 4G devices and the largest fabless semiconductor company in the world. The Graphics team is looking for an Engineer to work on QUALCOMMs Adreno Graphics cores in the area of implementation and methodology. The successful candidate will work in Adreno GPU team and will be responsible for various functions from RTL integration through to physical design.

As a member of the Graphics team, the successful applicant will help integrate, implement and develop state of the art GPU cores and will be working closely with the graphics microarchitecture and physical design teams. The successful candidate will possess basic understanding of RTL design and ASIC design flow from RTL to GDS2 such as synthesis, static timing analysis, formal verification, physical design and ECO generation and verification.

Knowledge and Experience

• Verilog and System‑Verilog languages
• RTL integration, partitioning, transformation, and analysis.
• Ensure implementation readiness with RTL lint, custom checks, unit level synthesis and clock domain crossing checks.
• Package, qualify and deliver FE design collateral.
• Develop innovative methods to improve front‑end design integration process.
• Collaborate effectively with Architecture, Design, DV, SOC, DFT, and IMPL teams spanning multiple sites.
• Version control systems
• RTL synthesis using physically aware tools
• Formal Verification using industry standard tools for RTL‑netlist and netlist‑netlist checks
• ECO methods for functional and timing fixes
• Managing design goals in power, performance and area

Minimum Skills

• 0-5 years relevant industry experience
• Digital design and RTL development understanding using Verilog and/or System Verilog
• Basic level knowledge of synthesis, static timing, timing closure, constraints and formal verification
• Exposure to Synopsys Design Compiler tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTime

Preferred Skills

• Experience with UNIX, Perl, TCL or shell scripting
• Ability to analyze architectural and micro architectural details to drive design partitioning.
• Knowledge of PPA optimization techniques, Power Intent (UPF/CPF), CDC, RDC, synthesis, physical design and STA.
• Excellent interpersonal and analytical skills as well as ability to work independently
• Highly motivated, excellent team spirit, obsession with deliverable quality and customer oriented

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

EEO Statement

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail [e-mail] or call Qualcomm's toll-free number. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

Pay Range and Other Compensation & Benefits

$161,800.00 - $242,600.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunities for annual RSU grants. In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.

Contact

If you would like more information about this role, please contact Qualcomm Careers.