GPU PPA Methodology Engineer (RTL to GDS)

Qualcomm; San Diego (CA); On-site; USD 170,000 - 254,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego, CA seeks a skilled engineer to advance PPA for state-of-the-art GPU cores. You will help develop flows, methodologies and algorithms while coordinating with graphics design and implementation teams to drive RTL-to-GDS improvements.

The role requires knowledge of RTL/ASIC design flow, Verilog/SystemVerilog and familiarity with EDA tools. Collaboration and problem-solving in a fast-paced environment are essential.

Qualifications

• Bachelor's degree in CE/CS/EE with 4+ years of related experience.
• Master's degree in CE/CS/EE with 3+ years of related experience.
• PhD in CE/CS/EE with 2+ years of related experience.

Responsibilities

• Develop flows, methodologies and algorithms to improve PPA on GPU cores.
• Collaborate with design, technology, power, implementation, sign-off and post-silicon teams.
• Understand RTL to GDS flow and apply improvements to GPU RTL/netlist paths.

Skills

Verilog

SystemVerilog

Python

UNIX shell

Perl

TCL

Education

Bachelors in CE/CS/EE

Masters in CE/CS/EE

PhD in CE/CS/EE

Tools

Synopsys Fusion Compiler

Synopsys RTL-Architect

PrimePower

PrimeTime

Prime Closure

Job description

Qualcomm Technologies, Inc. in San Diego, CA seeks a skilled engineer to advance PPA for state-of-the-art GPU cores. You will help develop flows, methodologies and algorithms while coordinating with graphics design and implementation teams to drive RTL-to-GDS improvements.

The role requires knowledge of RTL/ASIC design flow, Verilog/SystemVerilog and familiarity with EDA tools. Collaboration and problem-solving in a fast-paced environment are essential.