Senior Full-Chip Verification Engineer, Silicon

SpaceX; Sunnyvale (CA); On-site; USD 170,000 - 230,000; Full time

Benefits offered by this job

Comprehensive medical, vision, and dental coverage

401(k) retirement plan

Paid parental leave

Three weeks of paid vacation

Job summary

SpaceX in Sunnyvale is seeking a Sr. Full Chip Physical Verification Engineer to lead the physical verification of advanced silicon designs for the Starlink project. The ideal candidate will have over 5 years of relevant experience, proficiency with tools like Calibre and ICV, and a degree in electrical engineering. The position offers a competitive salary of $170,000 to $230,000 per year, along with comprehensive benefits including stock options and medical coverage.

Qualifications

• 5+ years of ASIC and/or physical design flow development experience in industry.
• Experience with SOC top-level physical design flows.
• Deep expertise in DRC, LVS, PERC and ESD verification methodologies.

Responsibilities

• Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools.
• Develop and optimize physical verification flows for advanced node SoCs.
• Engage directly with foundry teams to resolve DRM ambiguities.

Skills

ASIC design flow development

Physical verification methodologies

Scripting skills (Python, Perl, etc.)

Education

Bachelor's degree in electrical/computer engineering or computer science

Tools

Calibre

ICV

Pegasus

Job description

SpaceX in Sunnyvale is seeking a Sr. Full Chip Physical Verification Engineer to lead the physical verification of advanced silicon designs for the Starlink project. The ideal candidate will have over 5 years of relevant experience, proficiency with tools like Calibre and ICV, and a degree in electrical engineering. The position offers a competitive salary of $170,000 to $230,000 per year, along with comprehensive benefits including stock options and medical coverage.