Senior Full-Chip PV Engineer (Tapeout Ready)

Spacex; Palo Alto (CA); On-site; USD 175,000 - 280,000; Full time

Benefits offered by this job

Stock options

Long‑term incentives

Health, vision and dental coverage

Job summary

SpaceX is seeking a Sr. Full Chip Physical Verification Engineer to drive signoff of full‑chip DRC, LVS, ESD and PERC for advanced node SoCs used in Starlink and space platforms.

You will collaborate with cross‑functional teams and foundries to implement DRM rules and ensure robust tapeout readiness. The role requires 5+ years in ASIC/physical design, strong scripting, and hands‑on tool experience with Calibre, IC Validator, or Pegasus.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 5+ years of ASIC and/or physical design flow development experience in industry.
• Strong scripting skills (e.g. Python, Perl, TCL).
• Experience with SOC top level physical design flows and IP integration.

Responsibilities

• Own and sign off full‑chip DRC, LVS, ESD, PERC and antenna verification.
• Develop, maintain, and optimize physical verification flows for SoCs.
• Coordinate with foundries to implement DRM updates and resolve issues.
• Debug DRC/LVS violations across hierarchical full‑chip designs.
• Perform ESD verification and CDM/HBM compliance checks.
• Drive tapeout readiness and signoff across blocks and top‑level designs.

Skills

ASIC design

Scripting

Education

Bachelor’s degree in electrical/computer engineering or computer science

Tools

Calibre

ICV

Pegasus

Job description

SpaceX is seeking a Sr. Full Chip Physical Verification Engineer to drive signoff of full‑chip DRC, LVS, ESD and PERC for advanced node SoCs used in Starlink and space platforms.

You will collaborate with cross‑functional teams and foundries to implement DRM rules and ensure robust tapeout readiness. The role requires 5+ years in ASIC/physical design, strong scripting, and hands‑on tool experience with Calibre, IC Validator, or Pegasus.