Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SPACE EXPLORATION TECHNOLOGIES CORP; Sunnyvale (CA); On-site; USD 170,000 - 230,000; Full time

Benefits offered by this job

Comprehensive medical, vision, and dental coverage

401(k) retirement plan

Paid parental leave

Paid vacation (approximately 3 weeks)

Discretionary bonuses

Job summary

SPACE EXPLORATION TECHNOLOGIES CORP in Sunnyvale, CA is seeking a Sr. Full Chip Physical Verification Engineer to drive cutting-edge silicon integration for space technologies. Responsibilities include executing full-chip DRC, LVS, and ESD signoff, while using tools like Calibre and ICV. Candidates should have 5+ years in ASIC design and a Bachelor's in electrical/computer engineering. The role offers a competitive salary range of $170,000 to $230,000, comprehensive benefits, and long-term incentives.

Qualifications

• 5+ years of ASIC and/or physical design flow development experience in industry.
• Experience with large SOC designs (>10 M gates) at frequencies in excess of 1 GHz.

Responsibilities

• Own and execute full‑chip DRC, LVS, ESD, PERC, and antenna signoff.
• Engage directly with foundry teams to resolve DRM ambiguities.
• Develop/modify design flows to meet overall design quality requirements.

Skills

ASIC and physical design flow development

DRC, LVS, ESD, PERC verification

Proficiency with Calibre, ICV, Pegasus

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Tools

Calibre

ICV (IC Validator)

Pegasus

Job description

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

Sunnyvale, CA

SpaceX is actively developing technologies to make human life on Mars possible. We are building rockets, spacecraft, and Starlink – the world’s largest satellite constellation. We seek an engineer to work on next‑generation silicon for space and ground infrastructures, enabling connectivity where reliability and affordability have been lacking.

Responsibilities

• Own and execute full‑chip DRC, LVS, ESD, PERC, and antenna signoff using industry standard tools such as Calibre, ICV, or Pegasus.
• Develop, maintain, and optimize physical verification flows for advanced‑node SoCs.
• Interpret and implement foundry Design Rule Manuals (DRM) – translate rule updates into verified flow changes.
• Debug and resolve complex DRC/LVS violations across hierarchical full‑chip designs.
• Perform ESD verification – validate protection strategies, current paths, and CDM/HBM compliance.
• Drive tapeout readiness by coordinating signoff across block, top‑level, and hard IP design teams.
• Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
• Develop/modify design flows as needed to meet overall design quality of results and chip integration requirements.
• Leverage AI agents to automate rule‑deck validation, violation triage, and signoff reporting workflows.

Basic Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of ASIC and/or physical design flow development experience in industry.

Preferred Skills and Experience

• Deep understanding of SOC top‑level physical design flows (floor‑planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning).
• Experience in IP integration (memories, I/O, analog IPs, SerDes, DDR, etc.).
• Expertise in DRC, LVS, PERC, and ESD verification methodologies.
• Hands‑on proficiency with Calibre, ICV (IC Validator), or Pegasus.
• Direct foundry DRM experience – able to read, interpret, and implement complex rule decks.
• Experience at advanced nodes (4 nm and below).
• Experience with large SOC designs (>10 M gates) at frequencies in excess of 1 GHz.
• Self‑driven individual with a can‑do attitude and ability to work in a dynamic team environment.

Additional Requirements

• Ability to work extended hours and weekends as needed to meet critical project milestones.

Compensation & Benefits

Pay range: Physical Design Engineer/Senior: $170,000.00 – $230,000.00 per year. The final salary will be based on job‑related qualifications, education, and experience.

In addition to base salary, eligible employees may receive long‑term incentives in the form of stock, stock options, or cash awards, along with discretionary bonuses. Benefits include comprehensive medical, vision, and dental coverage; 401(k) retirement plan; short‑ and long‑term disability insurance; life insurance; paid parental leave; paid vacation (approximately 3 weeks), paid holidays, and sick leave.

Equal Opportunity and Endorsements

SpaceX is an Equal Opportunity Employer. Employment with SpaceX is governed on the basis of merit, competence, and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin or ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability, or any other legally protected status.

Applicants requiring reasonable accommodation for the application or interview process should contact [e-mail].