Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

InvestedintheMission; Irvine (CA); On-site; USD 160,000 - 225,000; Full time

Benefits offered by this job

Comprehensive medical, vision, and dental coverage

401(k) retirement plan

Paid parental leave

Various other discounts and perks

Job summary

jobr.pro is looking for a Sr. Full Chip Physical Verification Engineer in Irvine, California. This role involves executing full-chip DRC, LVS, and ESD signoff while working on cutting-edge silicon technologies that support the Starlink network.

The ideal candidate has a Bachelor's degree in a relevant field and over 5 years of ASIC design experience with expertise in design verification methodologies. Competitive compensation includes comprehensive benefits and stock options.

Qualifications

• 5+ years of ASIC and/or physical design flow development experience in industry.
• Deep expertise in DRC, LVS, PERC and ESD verification methodologies.
• Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.).

Responsibilities

• Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools.
• Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs.
• Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.

Skills

ASIC design flow development

physical design flows

DRC verification

LVS verification

scripting skills

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Calibre

ICV (IC Validator)

Pegasus

Job description

SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES

• Own and execute full‑chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus.
• Develop, maintain, and optimise physical verification flows for advanced node SoC’s.
• Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes.
• Debug and resolve complex DRC/LVS violations across hierarchical full‑chip designs.
• Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance.
• Drive tape‑out readiness by coordinating signoff across block and top‑level and Hard IP design teams.
• Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
• Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.
• Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows.

BASIC QUALIFICATIONS

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 5+ years of ASIC and/or physical design flow development experience in industry.

PREFERRED SKILLS AND EXPERIENCE

• Experience and deep understanding of SOC top‑level physical design flows (floor‑planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation).
• Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.).
• Deep expertise in DRC, LVS, PERC and ESD verification methodologies.
• Hands‑on proficiency with Calibre, ICV (IC Validator), or Pegasus.
• Direct foundry DRM experience — able to read, interpret, and implement complex rule decks.
• Experience at advanced nodes (4nm and below).
• Experience with large SOC designs (>10M gates) with frequencies in excess of 1 GHz.
• Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.).
• Self‑driven individual with a can‑do attitude, and an ability to work in a dynamic group environment.

ADDITIONAL REQUIREMENTS

• Ability to work extended hours and weekends as needed to meet critical project milestones.

COMPENSATION AND BENEFITS

Physical Design Engineer/Senior: $160,000.00 – $225,000.00 per year. Your actual level and base salary will be determined on a case‑by‑case basis and may vary based on job‑related knowledge and skills, education, and experience. Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long‑term incentives, in the form of company stock, stock options, or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short‑ and long‑term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

ITAR REQUIREMENTS

To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident (aka green card holder), (iii) refugee under 8 U.S.C. § 1157, or (iv) asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorisations from the U.S. Department of State. Learn more about the ITAR here.