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jobr.pro is looking for a Sr. Full Chip Physical Verification Engineer in Irvine, California. This role involves executing full-chip DRC, LVS, and ESD signoff while working on cutting-edge silicon technologies that support the Starlink network.
The ideal candidate has a Bachelor's degree in a relevant field and over 5 years of ASIC design experience with expertise in design verification methodologies. Competitive compensation includes comprehensive benefits and stock options.
jobr.pro is looking for a Sr. Full Chip Physical Verification Engineer in Irvine, California. This role involves executing full-chip DRC, LVS, and ESD signoff while working on cutting-edge silicon technologies that support the Starlink network.
The ideal candidate has a Bachelor's degree in a relevant field and over 5 years of ASIC design experience with expertise in design verification methodologies. Competitive compensation includes comprehensive benefits and stock options.