Stand out for this role — generate a tailored resume and cover letter in about a minute.
Get past ATS filters
Benefits offered by this job
Comprehensive medical, vision, and dental coverage
401(k) retirement plan
Paid parental leave
Paid vacation (approximately 3 weeks)
Discretionary bonuses
Job summary
SPACE EXPLORATION TECHNOLOGIES CORP in Sunnyvale, CA is seeking a Sr. Full Chip Physical Verification Engineer to drive cutting-edge silicon integration for space technologies. Responsibilities include executing full-chip DRC, LVS, and ESD signoff, while using tools like Calibre and ICV. Candidates should have 5+ years in ASIC design and a Bachelor's in electrical/computer engineering. The role offers a competitive salary range of $170,000 to $230,000, comprehensive benefits, and long-term incentives.
Qualifications
5+ years of ASIC and/or physical design flow development experience in industry.
Experience with large SOC designs (>10 M gates) at frequencies in excess of 1 GHz.
Responsibilities
Own and execute full‑chip DRC, LVS, ESD, PERC, and antenna signoff.
Engage directly with foundry teams to resolve DRM ambiguities.
Develop/modify design flows to meet overall design quality requirements.
Skills
ASIC and physical design flow development
DRC, LVS, ESD, PERC verification
Proficiency with Calibre, ICV, Pegasus
Education
Bachelor’s degree in electrical engineering, computer engineering, or computer science
Tools
Calibre
ICV (IC Validator)
Pegasus
Job description
SPACE EXPLORATION TECHNOLOGIES CORP in Sunnyvale, CA is seeking a Sr. Full Chip Physical Verification Engineer to drive cutting-edge silicon integration for space technologies. Responsibilities include executing full-chip DRC, LVS, and ESD signoff, while using tools like Calibre and ICV. Candidates should have 5+ years in ASIC design and a Bachelor's in electrical/computer engineering. The role offers a competitive salary range of $170,000 to $230,000, comprehensive benefits, and long-term incentives.