Lead Full-Chip Physical Verification Engineer

Celero Communications, Inc.; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. seeks a Principal Physical Verification Engineer to own full chip PV execution and drive tapeout readiness in San Jose, CA. You will collaborate with Analog and Physical Design teams to ensure DRC/LVS cleanliness and robust IP delivery.

The role demands 7+ years in full-chip verification, hands-on experience with ICV or Calibre, and scripting in Tcl/Python to automate PV flows. This is a senior, on-site position with competitive salary.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications.
• Hands-on with ICV or Calibre and PV flows.
• Experience in advanced technology nodes is a plus.

Responsibilities

• Lead full chip Physical Verification effort.
• Own execution plans, schedules for full-chip.
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks.

Skills

Full-chip PV execution

ICV/Calibre

Scripting Tcl/Python

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

ICV/Calibre

Job description

Celero Communications, Inc. seeks a Principal Physical Verification Engineer to own full chip PV execution and drive tapeout readiness in San Jose, CA. You will collaborate with Analog and Physical Design teams to ensure DRC/LVS cleanliness and robust IP delivery.

The role demands 7+ years in full-chip verification, hands-on experience with ICV or Calibre, and scripting in Tcl/Python to automate PV flows. This is a senior, on-site position with competitive salary.