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Broadcom seeks an experienced engineer to lead frontend design and verification for core ASIC blocks. You will architect, design, synthesize and constrain RTL, then verify with simulation and formal methods while analyzing timing across high-frequency process nodes.
The role requires strong RTL knowledge, system-level thinking, and collaboration across geographies. Broadcom offers a robust compensation package and comprehensive benefits.
Broadcom seeks an experienced engineer to lead frontend design and verification for core ASIC blocks. You will architect, design, synthesize and constrain RTL, then verify with simulation and formal methods while analyzing timing across high-frequency process nodes.
The role requires strong RTL knowledge, system-level thinking, and collaboration across geographies. Broadcom offers a robust compensation package and comprehensive benefits.