Design Engineering Director

Cadence Design Systems; Austin (TX); On-site; USD 180,000 - 270,000; Full time

Job summary

Cadence Design Systems is seeking an experienced leader to drive Front End design projects in the North America team. You will mentor RTL engineers, define microarchitectural features for IPs and subsystems, and oversee RTL development, verification, and signoff to ensure on-time delivery.

The role emphasizes collaboration with DV, PD, architecture, and firmware teams. The position targets a seasoned engineer with 10+ years in Front End design/verification, strong leadership, and a track record

Qualifications

• 10+ years of Front End design and/or verification experience with a BS/MS in Engineering or Computer Sciences.
• Proven track record leading and managing complex engineering projects.
• Rich experience in IP creation and/or SoC and IP integration.

Responsibilities

• Lead and mentor a team of RTL design engineers to deliver high-quality front end design solutions.
• Define and develop microarchitectural features for IPs and subsystems to meet PPA goals.
• Oversee RTL development, verification, and signoff including Lint, CDC, and FV.

Skills

RTL design

Leadership

IP integration

Verilog/SystemVerilog

Synthesis/PD/STA

Education

BS/MS Engineering

Tools

Cadence front end toolset

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry. This is a leadership role where you will be responsible for: Technical Leadership: Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals. RTL Development: Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic. Verification & Signoff: Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks. Collaboration: Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.

Qualifications

• 10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences
• Proven experience in leading and managing complex engineering projects
• Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
• Expert in RTL design (Verilog), simulators debuggers
• Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
• Experience in driving results in multi-disciplinary organization

Desirable

A Self-motivated person with good communication and design management skills Experience with Cadence front end toolset

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.