Senior FPGA & SDR Systems Engineer

Qualis LLC; Huntsville (AL); On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Health insurance

401(k) match

Paid time off

Education reimbursement

Tax savings

Life insurance

Job summary

Qualis LLC seeks an experienced FPGA/Digital Design Engineer to develop high-performance FPGA solutions for RF and SDR systems. You will implement in AMD/Xilinx devices using Vivado, VHDL/Verilog, and SystemVerilog, while building real-time DSP pipelines and optimized data movement.

The role emphasizes integrating reference designs, BSPs, and PetaLinux-based software, along with Tcl scripting for automation and board bring-up. Collaboration across RF, software, and hardware teams is essential.

Qualifications

• ABET-accredited degree in Electrical/Computer Engineering, Physics, or related field.
• 8+ years of FPGA-based development experience.
• Hands-on AMD/Xilinx FPGA devices and Vivado experience.
• Proficiency in VHDL/Verilog; SystemVerilog a plus.
• Experience implementing DSP algorithms in FPGA architectures.
• Experience with FPGA reference designs, IP cores, BSPs, and high-speed interfaces.
• Experience Tcl scripting for Vivado automation and bitstream generation.
• Experience with PetaLinux, embedded Linux development for FPGA systems.

Responsibilities

• Design, develop, integrate, and test FPGA-based processing solutions for RF and SDR systems.
• Develop FPGA designs using VHDL, Verilog, SystemVerilog in AMD/Xilinx Vivado.
• Optimize real-time DSP functions, data movement architectures, and processing pipelines.
• Integrate FPGA reference designs, IP cores, BSPs, and development platforms.
• Develop Tcl scripts to automate Vivado workflows and bitstream generation.
• Develop and integrate embedded Linux solutions with PetaLinux, including device trees and drivers.
• Configure FPGA interfaces for high-speed peripherals and RF components.
• Support board bring-up, debugging, timing closure, and lab validation.
• Collaborate with RF/software/hardware teams on integrated solutions.
• Contribute to architecture studies and future SDR/EW/PNT roadmaps.

Skills

FPGA development

VHDL

Verilog

SystemVerilog

Tcl scripting

Vivado

PetaLinux

Embedded Linux

Education

ABET-accredited degree (Electrical/Computer Engineering or related)

Bachelors degree

Tools

Vivado

PetaLinux

Vitis

Job description

Qualis LLC seeks an experienced FPGA/Digital Design Engineer to develop high-performance FPGA solutions for RF and SDR systems. You will implement in AMD/Xilinx devices using Vivado, VHDL/Verilog, and SystemVerilog, while building real-time DSP pipelines and optimized data movement.

The role emphasizes integrating reference designs, BSPs, and PetaLinux-based software, along with Tcl scripting for automation and board bring-up. Collaboration across RF, software, and hardware teams is essential.