RF FPGA Engineer - Embedded DSP & HW Design

Epirus; Torrance (CA); On-site; USD 102,000 - 118,000; Full time

Job summary

Epirus in California is seeking a hands-on FPGA design engineer to design, verify, and integrate state‑of‑the‑art FPGA systems and embedded processing solutions for RF applications. You will collaborate with a multi-disciplinary team to deliver novel RF systems for rapid development.

The role emphasizes RTL design, board bring-up, test automation, and documenting design tradeoffs. A BS in EE, 2+ years, and Vivado/Quartus experience are required; SystemVerilog/UVM and high-speed interfaces are a

Qualifications

• BS degree in Computer or Electrical engineering.
• 2+ years of technical experience.
• Familiarity implementing FPGA and microprocessor designs on embedded hardware.
• Experience with Vivado and Quartus toolchains.
• Understanding SPI, I2C, UART protocols.
• Strong written and oral communication; collaborative.
• US Citizen and/or PR with eligibility for security clearance.

Responsibilities

• Design and verification of RTL modules for FPGA applications.
• Initial test and bring-up of custom FPGA circuit cards with peripherals.
• Automation of test environment and measurement devices.
• Capturing design tradeoffs, state machine flow, address maps, and block diagrams.

Skills

FPGA design

Embedded hardware

Vivado

Quartus

Verilog/VHDL

SystemVerilog/UVM

SPI/I2C/UART

Communication skills

Collaborative

Organized

Education

BS in Computer or Electrical engineering

MS in Computer or Electrical engineering

Tools

Vivado

Quartus

SystemVerilog/UVM

Verilog/VHDL

Job description

Epirus in California is seeking a hands-on FPGA design engineer to design, verify, and integrate state‑of‑the‑art FPGA systems and embedded processing solutions for RF applications. You will collaborate with a multi-disciplinary team to deliver novel RF systems for rapid development.

The role emphasizes RTL design, board bring-up, test automation, and documenting design tradeoffs. A BS in EE, 2+ years, and Vivado/Quartus experience are required; SystemVerilog/UVM and high-speed interfaces are a