Senior FPGA/RTL Design Engineer for Wireless Systems

Silvus Technologies; California; Hybrid; USD 100,000 - 140,000; Full time

Job summary

Silvus Technologies seeks a Senior FPGA / RTL Design Engineer to join the FPGA Engineering team in West Los Angeles, CA. The role involves designing signal processing blocks for MIMO wireless systems, RTL coding, and FPGA timing closure, reporting to the Director of FPGA Engineering.

The position is hybrid with at least 3 days onsite weekly (Mon/Wed/Thu). U.S. person status is required for federal contracts; the company emphasizes equal opportunity employment and a strong, hero-focused culture.

Qualifications

• Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant fields.
• Minimum 6 years of demonstrated experience in FPGA design; 4 years of FPGA design experience with a Master's of Science degree; 2 years of FPGA design experience with a PhD degree.
• Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
• Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Must be a U.S. Person (U.S. Citizen, or U.S. Permanent Resident) due to clients under U.S. federal contracts.

Responsibilities

• Digital design architecting for wireless communication projects.
• Fixed point design of signal processing blocks while working with systems engineers.
• RTL coding, simulation, and test bench development.
• FPGA synthesis and timing closure.
• Hardware verification and troubleshooting; familiarity with logic analyzers.
• Provide support to the RF and Software Engineering teams.

Skills

Digital design

Fixed-point DSP

Clock-domain design

FPGA design

Education

B.S. Electrical Engineering / CS

MS in Electrical Engineering

Tools

Xilinx FPGAs/SoCs

Vivado IDE

Job description

Silvus Technologies seeks a Senior FPGA / RTL Design Engineer to join the FPGA Engineering team in West Los Angeles, CA. The role involves designing signal processing blocks for MIMO wireless systems, RTL coding, and FPGA timing closure, reporting to the Director of FPGA Engineering.

The position is hybrid with at least 3 days onsite weekly (Mon/Wed/Thu). U.S. person status is required for federal contracts; the company emphasizes equal opportunity employment and a strong, hero-focused culture.