Senior FPGA/ASIC Design Engineer with Security Clearance

The Fountain Group; El Segundo (CA); On-site; USD 132,000 - 179,000; Full time

Job summary

The Fountain Group in El Segundo, CA is seeking an experienced FPGA/ASIC Design Engineer for a 6-month assignment. The role focuses on developing and integrating digital hardware, with strong Xilinx Vivado experience and SystemVerilog proficiency.

Openings: 10. Active U.S. Secret Security Clearance is required to start. A Bachelor’s degree in Engineering, CS, Mathematics, Physics or related field is required, with 5+ years of FPGA/ASIC design experience.

Qualifications

• 5+ years of FPGA/ASIC design experience.
• Strong Xilinx/AMD Vivado experience.
• Experience with Xilinx Versal devices.
• Proficiency with Verilog/SystemVerilog HDL.
• Advanced FPGA implementation skills: synthesis, timing closure, constraints.
• Active U.S. Secret Security Clearance required to start.
• Bachelor’s degree in Engineering, CS, Math, Physics, or related field.

Responsibilities

• Develop and integrate new FPGA functional blocks and interfaces.
• Integrate third-party and in-house IP cores.
• Perform synthesis, simulation, Place & Route, and timing closure.
• Update FPGA constraint files and program FPGA devices.
• Support hardware/software system integration and testing.
• Collaborate with engineering teams to deliver production-ready solutions.

Skills

FPGA design

ASIC design

Verilog/SystemVerilog

Vivado

Timing closure

Security clearance

Education

Bachelor’s degree in Engineering/CS/Math/Physics/related field

Tools

Vivado tools

Place & Route

Synthesis

Job description

The Fountain Group in El Segundo, CA is seeking an experienced FPGA/ASIC Design Engineer for a 6-month assignment. The role focuses on developing and integrating digital hardware, with strong Xilinx Vivado experience and SystemVerilog proficiency.

Openings: 10. Active U.S. Secret Security Clearance is required to start. A Bachelor’s degree in Engineering, CS, Mathematics, Physics or related field is required, with 5+ years of FPGA/ASIC design experience.