Senior FPGA Engineer: Space-grade DSP & SDR (Remote/Hybrid)

AscendArc; Portland (OR); Hybrid; USD 150,000 - 210,000; Full time

Job summary

AscendArc in Portland, OR is seeking a Senior FPGA Developer to own RTL design across DSP, SDR, and spacecraft interfaces. You will lead integration of IP cores, develop custom DSP blocks, and drive RTL verification from design to orbit.

You will work with systems, firmware, and hardware teams, write verification testbenches (UVM/cocotb), and navigate timing closure in Vivado. This role demands hands‑on ownership, strong FPGA/ DSP fundamentals, and experience with high‑speed serial transceivers.

Qualifications

• BS/MS in EE/CE or equivalent experience.
• 8+ years FPGA development in SystemVerilog/VHDL.
• Experience integrating third‑party IP cores into FPGA designs.
• Understand packet‑based routing and switching concepts.
• Strong DSP fundamentals and fixed‑point HDL experience.
• Experience with high‑speed serial transceivers (8b/10b, 64b/66b).
• Proficiency with Vivado toolchain and constraint writing.
• Strong verification skills and Git workflows.

Responsibilities

• Architect, write, and verify synthesizable RTL (SystemVerilog or VHDL) targeting modern FPGAs.
• Integrate and configure existing modulation, demodulation, and packet‑switching IP cores; configure ports, routing, and interfaces; validate end‑to‑end behavior.
• Develop simulation testbenches (UVM, cocotb or similar); drive functional and code coverage; bring designs through synthesis, place‑and‑route, and timing closure; analyze utilization and Fmax; RTL fixes.
• Integrate with ADC/DAC front‑ends and mixed‑signal interfaces, including clocking, calibration, and lane alignment.
• Collaborate with systems, firmware, and hardware engineers on interface definitions and HW/SW partitioning; produce design docs, interface control documents, and verification reports.

Skills

FPGA development (SystemVerilog/VHDL)

IP core integration

Packet routing concepts

DSP in HDL fixed‑point

High‑speed serial transceivers (8b/10b

Vivado toolchain

Verification & Git workflows

Education

B.S. or M.S. in Electrical Engineering or Computer Engineering

Tools

Vivado

Job description

AscendArc in Portland, OR is seeking a Senior FPGA Developer to own RTL design across DSP, SDR, and spacecraft interfaces. You will lead integration of IP cores, develop custom DSP blocks, and drive RTL verification from design to orbit.

You will work with systems, firmware, and hardware teams, write verification testbenches (UVM/cocotb), and navigate timing closure in Vivado. This role demands hands‑on ownership, strong FPGA/ DSP fundamentals, and experience with high‑speed serial transceivers.