Real-time Space FPGA DSP/SDR Engineer

Remote; San Francisco (CA); Remote; USD 120,000 - 190,000; Full time

Job summary

Kepler Communications is seeking an experienced FPGA Digital Design Engineer to help build the next generation of our satellite payloads. You will design and implement FPGA code, focusing on DSP algorithms for on-board SDR processing or embedded interfaces, and participate in all stages of the FPGA design flow from simulation to hardware testing.

The role requires a Bachelor's in Computer or Electrical Engineering and 5+ years of FPGA/RTL experience, plus Proficiency in Verilog/SystemVerilog,

Qualifications

• Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent.
• 5+ years of FPGA/RTL design experience.
• Proficiency in Verilog, SystemVerilog, or VHDL; willingness to pivot to SystemVerilog.
• Experience with Xilinx FPGAs, specifically Zynq and UltraScale.
• Solid understanding of timing principles including clock domain crossing and timing closure.
• Strong scripting skills (e.g. Python, Tcl, Bash).
• Experience with FPGA tools (Vivado, Quartus) and HDL simulation tools (ModelSim).

Responsibilities

• Develop custom IP for new features of the Kepler satellite digital payloads
• Iterate on current DSP and interface designs to improve reliability
• Work with IP core vendors to integrate new functionality into the Kepler designs
• Work with lead engineers in developing the communications and network architecture of our future satellite constellation
• Participate in conceptual design studies of new spacecraft

Skills

FPGA RTL design

Verilog/SystemVerilog

Xilinx FPGAs

Timing closure

Scripting languages

EDA tools

DSP concepts

Education

Bachelor's in Computer/Electrical Engineering

Tools

Vivado

Quartus

ModelSim

Job description

Kepler Communications is seeking an experienced FPGA Digital Design Engineer to help build the next generation of our satellite payloads. You will design and implement FPGA code, focusing on DSP algorithms for on-board SDR processing or embedded interfaces, and participate in all stages of the FPGA design flow from simulation to hardware testing.

The role requires a Bachelor's in Computer or Electrical Engineering and 5+ years of FPGA/RTL experience, plus Proficiency in Verilog/SystemVerilog,