Senior FPGA Architect — Satellite SDR & DSP (Remote)

AscendArc; Beaverton (OR); Hybrid; USD 180,000 - 230,000; Full time

Job summary

AscendArc in Beaverton, OR is seeking a Senior FPGA Developer to own RTL development across FPGA, DSP, SDR, and spacecraft integration.

You will work with existing IP cores, implement DSP blocks, validate end-to-end behavior, and bring designs from concept to orbit, collaborating with systems, firmware, and hardware engineers.

This role offers technical ownership, hands-on design, debugging, and a path to influence the architecture of next-generation communications.

Qualifications

• 8+ years of professional FPGA development in SystemVerilog and/or VHDL.
• Experience integrating third-party IP cores into FPGA designs—reading datasheets, configuring parameters, and verifying integration.
• Understanding of packet-based routing and switching concepts for integrating and debugging routing IP.

Responsibilities

• Architect, write, and verify synthesizable RTL targeting modern FPGAs.
• Integrate and configure existing modulation/demodulation, and packet-switching IP cores with parameterized ports and routing tables.
• Implement DSP blocks in fabric: FIR/CIC/polyphase filters, NCOs, mixers, decimation/interpolation, channelizers, and demodulation/synchronization logic.
• Develop simulation testbenches (UVM, cocotb) and drive functional and coverage; bring designs through synthesis, place-and-route, timing closure.
• Analyze utilization, congestion, and Fmax issues; resolve RTL-level problems; integrate with ADC/DAC interfaces and clocking.
• Collaborate with systems, firmware, and hardware engineers on interface definitions and HW/SW partitioning; produce verification reports.

Skills

SystemVerilog

VHDL

FPGA design

DSP fundamentals

High-speed transceivers

Vivado toolchain

Verification

Education

B.S. or M.S. in Electrical Engineering or Computer Engineering

Tools

UVM

Cocotb

Git

Xilinx Vivado

Job description

AscendArc in Beaverton, OR is seeking a Senior FPGA Developer to own RTL development across FPGA, DSP, SDR, and spacecraft integration.

You will work with existing IP cores, implement DSP blocks, validate end-to-end behavior, and bring designs from concept to orbit, collaborating with systems, firmware, and hardware engineers.

This role offers technical ownership, hands-on design, debugging, and a path to influence the architecture of next-generation communications.