Senior FPGA Engineer — RTL/Timing Closure, Hybrid PA

Actalent; Newtown (PA); Hybrid; USD 76,000 - 92,000; Full time

Job summary

Actalent in Newtown, PA seeks an experienced FPGA Engineer to design, develop, test, and deploy FPGA-based products. The role targets 7–10 years of RTL design, FPGA development, simulation, verification, timing closure, and product development support.

You will work with hardware, embedded software, and test engineers in a dynamic, collaborative environment, focusing on high-speed FPGA projects and lab debugging to ensure successful deployments.

Qualifications

• 7–10 years of FPGA RTL design and development experience.
• Experience with FPGA simulation/verification before hardware deployment.
• Proven track record delivering FPGA designs into production.
• Strong timing closure and synchronization skills.
• Experience with Xilinx is preferred; Microchip/Intel/Altera also valuable.

Responsibilities

• Design and develop FPGA-based products focusing on RTL, FPGA development, and simulation.
• Collaborate with hardware, embedded software, and test engineers to ensure seamless product development.
• Perform simulation and verification to validate designs before hardware deployment.
• Achieve timing closure on high-speed FPGA designs through timing analysis and optimization.
• Provide product development support and engage in lab debugging and troubleshooting.

Skills

RTL design

FPGA development

Simulation

Verification

Timing analysis

Lab debugging

Python scripting

TCL scripting

Cross-functional collaboration

Tools

Xilinx FPGA

Intel/Altera

Microchip

Verilog/VHDL

FPGA design tools

Job description

Actalent in Newtown, PA seeks an experienced FPGA Engineer to design, develop, test, and deploy FPGA-based products. The role targets 7–10 years of RTL design, FPGA development, simulation, verification, timing closure, and product development support.

You will work with hardware, embedded software, and test engineers in a dynamic, collaborative environment, focusing on high-speed FPGA projects and lab debugging to ensure successful deployments.