Hybrid FPGA Engineer – RTL, Timing & Verification

Actalent; Tallahassee (FL); Hybrid; USD 76,000 - 92,000; Part time

Benefits offered by this job

Medical, dental & vision

401(k) Retirement Plan

Life Insurance

Short and long-term disability

Health Spending Account (HSA)

Transportation benefits

Employee Assistance Program

Time Off/Leave (PTO)

Job summary

Actalent is seeking an FPGA Engineer for a contract-to-hire role in Newtown, PA. You will design and develop FPGA-based products focusing on RTL design, simulation, and timing closure, collaborating with hardware, embedded software, and test teams to ensure robust production-ready solutions.

Ideal candidates bring hands-on FPGA design with VHDL/Verilog, experience achieving timing closure on high-speed parts, and scripting skills in Python or TCL to streamline build flows; a hybrid work setup is

Qualifications

• Hands-on FPGA design experience with production-ready designs.
• Proficient RTL coding with VHDL; Verilog acceptable.
• Experience achieving timing closure on high-speed FPGAs.

Responsibilities

• Design and develop FPGA-based products with RTL design, FPGA development, and simulation.
• Collaborate with hardware, embedded software, and test engineers to ensure seamless product development.
• Perform simulation and verification to validate designs before hardware deployment.
• Achieve timing closure on high-speed FPGA designs through timing analysis and optimization.

Skills

FPGA design

RTL coding (VHDL/Verilog)

Timing closure

FPGA simulation & verification

Xilinx familiarity

Tools

Python

TCL

Job description

Actalent is seeking an FPGA Engineer for a contract-to-hire role in Newtown, PA. You will design and develop FPGA-based products focusing on RTL design, simulation, and timing closure, collaborating with hardware, embedded software, and test teams to ensure robust production-ready solutions.

Ideal candidates bring hands-on FPGA design with VHDL/Verilog, experience achieving timing closure on high-speed parts, and scripting skills in Python or TCL to streamline build flows; a hybrid work setup is