FPGA Design Engineer – RTL, IP & Bring-up

Hewlett Packard Enterprise; Spring (TX); On-site; USD 74,000 - 170,000; Full time

Job summary

Hewlett Packard Enterprise in Texas is seeking an FPGA Design Engineer to develop RTL for FPGA/ CPLD designs, selecting parts and coordinating with firmware teams. You will simulate, synthesize, and validate timing in Verilog RTL while collaborating with hardware and software teams across diverse locations.

The role involves bring-up, testing, and occasional travel. The ideal candidate has a BS/MS in EE and 4+ years writing RTL for FPGA/ASIC projects, with experience in Xilinx Spartan 6/7 and

Qualifications

• Bachelor's or Master's degree in Electrical Engineering.
• 4+ years experience writing RTL for FPGAs for complex compute boards and/or ASIC designs.
• Experience with BMC controllers and hardware management interfaces is desired.
• Knowledge of server grade x86/ARM/GPU processors is desired.
• Experience with Xilinx Spartan 6/7 and Artix 7 families is desired.

Responsibilities

• Develop RTL for Xilinx (AMD) FPGA and/or Lattice CPLD designs.
• Select parts weighing cost, complexity, longevity, and expandability.
• Design hardware controls and sequencing for power, monitoring devices.
• Simulate, design, synthesize, and validate timing in Verilog RTL.
• Create IP for interface controllers and related functions.
• Review designs with design and operations teams and participate in reviews.
• Generate programming models and work with firmware on drivers.
• Collaborate with board engineers for bring-up and testing of PCBs.
• Lead or support debug of development and field issues; document resolutions.
• Work with partners/vendors to define requirements and co-development efforts.
• Coordinate with FPGA vendors to understand roadmaps and new IP developments.

Skills

Verilog RTL

Schematic reading

Communication skills

Team collaboration

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Xilinx FPGA tooling

Hardware debugging tools

Job description

Hewlett Packard Enterprise in Texas is seeking an FPGA Design Engineer to develop RTL for FPGA/ CPLD designs, selecting parts and coordinating with firmware teams. You will simulate, synthesize, and validate timing in Verilog RTL while collaborating with hardware and software teams across diverse locations.

The role involves bring-up, testing, and occasional travel. The ideal candidate has a BS/MS in EE and 4+ years writing RTL for FPGA/ASIC projects, with experience in Xilinx Spartan 6/7 and