Senior FPGA Engineer: RTL/DSP, SystemVerilog/VHDL (Irvine)

Actalent; California (MO); On-site; USD 110,000 - 152,000; Full time

Benefits offered by this job

Medical, dental & vision

401(k) Retirement Plan

Life Insurance

Short and long-term disability

Health Spending Account (HSA)

Transportation benefits

Employee Assistance Program

Time Off/Leave

Job summary

Actalent seeks an experienced FPGA Engineer to lead architecture, development and verification of FPGA-based subsystems in Irvine, CA. You will own the design from concept through qualification, verification, integration and manufacturing.

Responsibilities include defining FPGA architecture, RTL development in SystemVerilog or VHDL, and working with Vivado/Xilinx tools. This is a contract onsite role with competitive hourly pay.

Qualifications

• Extensive experience with FPGA, Verilog, VHDL, SystemVerilog.
• Proficiency in using Vivado and Xilinx tools.
• Strong background in digital design and DSP.
• 10+ years of FPGA RTL architecture, development, and verification.

Responsibilities

• Lead the architecture, development, and verification of FPGA-based subsystems.
• Own the design process from concept through qualification, verification, integration, and manufacturing.
• Define FPGA architecture and requirements.
• Develop RTL in SystemVerilog or VHDL.

Skills

FPGA RTL

Verilog

SystemVerilog

VHDL

Vivado

Xilinx tools

Digital design

DSP

10+ years

Tools

Vivado

Xilinx tools

Job description

Actalent seeks an experienced FPGA Engineer to lead architecture, development and verification of FPGA-based subsystems in Irvine, CA. You will own the design from concept through qualification, verification, integration and manufacturing.

Responsibilities include defining FPGA architecture, RTL development in SystemVerilog or VHDL, and working with Vivado/Xilinx tools. This is a contract onsite role with competitive hourly pay.