Senior FPGA & DSP Architect for Real-Time EW

Research Innovations Incorporated; Alexandria (VA); Hybrid; USD 150,000 - 210,000; Full time

Benefits offered by this job

401k with company match

Health insurance

Paid time off

Flexible work schedules

Job summary

Research Innovations Incorporated is seeking a Senior Principal FPGA & DSP Engineer to lead real-time FPGA-based signal processing for DoD, IC, and partner missions. You'll architect high-performance firmware, collaborate with hardware, software, AI, and RF teams, and translate advanced algorithms into deployable capabilities.

The role requires 10+ years FPGA/ DSP experience, VHDL/SystemVerilog, Vivado, RFSoC/Versal, and a TS/SCI–level clearance.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field; Master/PhD preferred.
• 10+ years FPGA development experience for RF, SDR, SIGINT, radar, or EW systems.
• Ownership of FPGA architecture from concept to production.
• Active Secret clearance; TS/SCI preferred.

Responsibilities

• Lead FPGA firmware architecture across FPGA, GPU, and CPU to meet latency, throughput, and SWaP requirements.
• Migrate GPU DSP algorithms to FPGA implementations with fixed-point optimization.
• Design reusable FPGA IP for AMD/Xilinx platforms (RFSoC, Versal, UltraScale+, Zynq).
• Develop real-time FPGA for RF DSP: DDC, filtering, FFTs, channelization, synchronization, demodulation.

Skills

FPGA architecture

VHDL/SystemVerilog

DSP

Python

C/C++

MATLAB

Git

Agile

Education

Bachelor's degree in EE/CE/CS

Master's or PhD preferred

Tools

Vivado

Vitis

RFSoC/Versal

RFNoC (optional)

JESD204B/C

Job description

Research Innovations Incorporated is seeking a Senior Principal FPGA & DSP Engineer to lead real-time FPGA-based signal processing for DoD, IC, and partner missions. You'll architect high-performance firmware, collaborate with hardware, software, AI, and RF teams, and translate advanced algorithms into deployable capabilities.

The role requires 10+ years FPGA/ DSP experience, VHDL/SystemVerilog, Vivado, RFSoC/Versal, and a TS/SCI–level clearance.