Principal FPGA Engineer — Secret Clearance, Space Systems

Northrop Grumman; Chandler (AZ); On-site; USD 108,000 - 162,000; Full time

Benefits offered by this job

Relocation assistance

Job summary

Northrop Grumman Space Systems in Chandler, AZ is seeking a Principal FPGA Digital Engineer to support the EO Group within the Launch Vehicles unit. You will develop and validate FPGA designs, test benches, and HDL modules, collaborating across hardware, algorithms, and software teams to meet timing and integration goals.

The role requires a strong background in FPGA/SoC design, VHDL or Verilog, and experience with Xilinx FPGAs, Vivado, and OSVVM/UVM.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering from an accredited university with required experience.
• Ability to obtain DoD Secret clearance at time of application.
• Strong FPGA/SoC design background with VHDL or Verilog.
• Experience with AMD Xilinx FPGAs and SoCs and timing analysis.
• Knowledge of MOSA interfaces/buses and hardware debugging tools.

Responsibilities

• Collaborate with senior FPGA engineers across hardware, algorithms, and software teams.
• Develop and execute advanced test benches to verify timing and functionality.
• Generate and integrate IO and image processing HDL modules with device architecture.
• Ensure compliance with design standards and manage multiple bitstream configurations.
• Prepare design documentation, verification reports, and maintain configuration management.
• Stay current with evolving FPGA technologies and industry methodologies.

Skills

FPGA design

VHDL/Verilog

Xilinx FPGAs/SoCs

OSVVM/UVM

Vivado IDE

Vitis

Questa/ModelSim

HDL test benches

Education

Bachelor’s degree in Electrical/Computer Engineering

5 years of relevant experience

Tools

Vivado IDE

Vitis Unified IDE

HDL simulators

Oscilloscopes/logic analyzers

Job description

Northrop Grumman Space Systems in Chandler, AZ is seeking a Principal FPGA Digital Engineer to support the EO Group within the Launch Vehicles unit. You will develop and validate FPGA designs, test benches, and HDL modules, collaborating across hardware, algorithms, and software teams to meet timing and integration goals.

The role requires a strong background in FPGA/SoC design, VHDL or Verilog, and experience with Xilinx FPGAs, Vivado, and OSVVM/UVM.