Elect Design and Analy Engr 5

The Adecco Group; El Segundo (CA); On-site; USD 131,000 - 164,000; Full time

Job summary

PDS Defense, Inc. in El Segundo, CA is seeking an Elect Design and Analy Engr 5 for FPGA/ASIC design work. The role focuses on FPGA top-level design, IP integration, synthesis, timing closure, and device programming, primarily Versal/UltraScale families.

The position requires on-site work in El Segundo, and candidates must hold an active U.S. security clearance. Ideal for engineers with strong digital hardware fundamentals and independent work style.

Qualifications

• 5+ years of FPGA and/or ASIC design experience.
• Strong Xilinx/AMD Vivado experience.
• Experience with Versal family devices.
• Verilog/SystemVerilog HDL proficiency required.
• Advanced FPGA implementation skills (synthesis, timing closure, constraints).
• Active U.S. security clearance

Responsibilities

• Inherit FPGA top-level design and create/add new blocks and interfaces including IP cores.
• Update constraint files and perform synthesis, simulation, and Place & Route to ensure timing closure.
• Program FPGA devices (Versal, UltraScale/UltraScale+) and verify design integrity.
• Collaborate with system engineering team for hardware/software integration and testing.
• On-site work is required.

Skills

FPGA/ASIC design

Vivado

Versal devices

Verilog/SystemVerilog

Timing closure

Active U.S. security clearance

Tools

Vivado

Job description

Job Details

PDS Defense, Inc. is seeking an Elect Design and Analy Engr 5, in El Segundo, CA. Job ID#224980

Posted:8/12/2026

Company: PDS Defense, Inc.

Job Title: Elect Design and Analy Engr 5

Location: El Segundo, CA

Job ID: 224980

Job Category: Engineering

Position Type: Associate - W2

Duration: 26

Positions Available: 10

Pay Rate: $95.00 - $119.00

Job Description

Regular and predictable attendance is required

Work statement is a non-managerial role, non-leadership role.

The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultra scale, and Ultra scale+ families.

Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system. Therefore, on-site work is required.

Required Skills

• 5+ years of FPGA and/or ASIC design experience;
• Strong Xilinx/AMD Vivado experience;
• Experience with Versal family devices;
• Verilog/System Verilog HDL proficiency required;
• Advanced FPGA implementation skills (synthesis, timing closure, constraints);
• Active U.S. security clearance

Preferred Skills

• 2+ years of FPGA design experience;
• Strong Xilinx/AMD Vivado experience;
• Verilog/System Verilog proficiency;
• Advanced FPGA implementation skills (synthesis, timing closure, constraints);

General Recruiting Guidance

Across all positions, we are looking for engineers who:

• Demonstrate strong digital hardware fundamentals.
• Exercise sound engineering judgment.
• Work independently with minimal oversight.
• Communicate clearly and proactively.
• Produce high-quality technical documentation.
• Take ownership of their work and deliver maintainable engineering solutions.
• Recruiters should prioritize candidates who can clearly explain their personal technical contributions, design decisions, debugging approach, and ownership of deliverables, rather than simply listing tools or technologies used on a project.

Benefits

• direct deposit
• free career counseling services
• 401(k)
• select paid holidays
• short-term disability insurance
• skills training
• employee referral bonus
• affordable medical coverage plan
• DailyPay (in some locations)

For a full description of benefits available to you, be sure to talk with your recruiter.

Job Requirements

Minimum Security Clearance: Secret

Military connected talent encouraged to apply.

Equal Opportunity Information

VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled

Candidate Privacy Information

To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/

Fair Chance

• The California Fair Chance Act
• Los Angeles City Fair Chance Ordinance
• Los Angeles County Fair Chance Ordinance for Employers
• San Francisco Fair Chance Ordinance