Senior FPGA DDR & IO Subsystem Architect

191 Altera Corporation; San Jose (CA); On-site; USD 200,400 - 286,000; Full time

Job summary

191 Altera Corporation is looking for a leading architect in High-Speed External Memory systems to develop innovative solutions. The role requires extensive experience in RTL design, memory technologies, and cross-functional collaboration.

The ideal candidate will possess a minimum of a Bachelor's Degree in Electrical Engineering and 10+ years of relevant experience. This position is based in San Jose, California and offers a competitive salary range of $200,400 – $286,000, along with performance-based incentives.

Qualifications

• 10+ years of hands-on experience in RTL design and ASIC design flows.
• Deep understanding of the latest SDRAM technologies.
• Experience architecting and delivering high-speed external memory subsystems.

Responsibilities

• Develop the architecture for High-Speed External Memory.
• Drive architectural trade-off analysis across performance, power, area.
• Engage with customers to understand requirements.

Skills

Verilog

SystemVerilog

C++

Python

DDR4/DDR5

LPDDR4/LPDDR5

Education

Bachelor’s Degree in Electrical Engineering

Master’s or Ph.D. in Electrical Engineering

Job description

191 Altera Corporation is looking for a leading architect in High-Speed External Memory systems to develop innovative solutions. The role requires extensive experience in RTL design, memory technologies, and cross-functional collaboration.

The ideal candidate will possess a minimum of a Bachelor's Degree in Electrical Engineering and 10+ years of relevant experience. This position is based in San Jose, California and offers a competitive salary range of $200,400 – $286,000, along with performance-based incentives.