Memory Validation Architect: DDR5/HBM & FPGA

Altera Corporation; San Jose, Northern (CA, KY); Hybrid; USD 210,000 - 303,000; Full time

Job summary

Altera seeks a Memory Validation Architect to define and lead validation architecture for memory subsystems across FPGA product families. You will drive validation planning from architecture through silicon bring-up, qualification, and customer deployment.

The role requires 15+ years in memory subsystems, DDR5/LPDDR5/HBM expertise, and strong leadership to mentor teams and shape product direction across multiple generations.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 15+ years of industry experience in memory subsystem architecture, silicon validation, high-speed interface development, or a related field.
• 10+ years of hands-on experience designing, validating, debugging, or optimizing DDR memory technologies (DDR4/5, LPDDR4/5, HBM).
• 8+ years of experience leading silicon bring-up, debugging, characterization, validation, and production qualification for complex SoCs or memory subsystems.
• 5+ years of programming or automation experience using Python, C/C++, or similar languages.
• 5+ years of experience leading cross-functional technical projects.

Responsibilities

• Define end-to-end validation architecture and strategy for memory subsystems across FPGA product families.
• Drive validation from architecture through silicon bring-up and qualification.
• Architect scalable validation frameworks and automation for multiple generations.
• Lead pre-silicon and post-silicon validation for DDR5, LPDDR5/HBM, memory controllers and PHYs.
• Establish metrics and lead investigations across RTL, firmware, board design and software.

Skills

Memory subsystem architecture

DDR memory technologies

Silicon bring-up

System validation

Cross-functional leadership

Python/C/C++ for automation

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or related field

Master's degree with 13+ years of experience

Ph.D. with 10+ years of experience

Tools

Oscilloscopes

Logic analyzers

BERTs

Protocol analyzers

Traffic generators

Job description

Altera seeks a Memory Validation Architect to define and lead validation architecture for memory subsystems across FPGA product families. You will drive validation planning from architecture through silicon bring-up, qualification, and customer deployment.

The role requires 15+ years in memory subsystems, DDR5/LPDDR5/HBM expertise, and strong leadership to mentor teams and shape product direction across multiple generations.