Memory Validation Architect - Lead, FPGA Memory Subsystems

altera; San Jose (CA); On-site; USD 210,000 - 303,000; Full time

Job summary

Altera is seeking an accomplished Memory Validation Architect to define and lead the validation architecture for DDR5, LPDDR5/LPDDR6, HBM, and future memory technologies across our FPGA portfolio. This high-visibility role collaborates with architecture, RTL, firmware, board design, and memory vendors to ensure industry-leading quality and interoperability.

You will mentor engineers, establish scalable validation methodologies, and drive validation from pre-silicon through production, focusing

Qualifications

• Experience leading memory validation programs for complex SoCs or FPGA platforms.
• Proven ability to design and implement scalable validation architectures.
• Excellent debugging and problem-solving skills across silicon and system levels.

Responsibilities

• Define end-to-end validation architecture and strategy for memory subsystems across multiple FPGA families.
• Drive validation planning from architecture through silicon bring-up, qualification, and customer deployment.
• Architect reusable validation frameworks and automation to support multiple generations.
• Lead pre-silicon and post-silicon validation for DDR5, LPDDR5/LPDDR6, and HBM; manage memory controllers and PHYs.
• Define comprehensive validation methodologies: functional correctness, performance, margining, reliability, stress testing, and interoperability.
• Establish silicon characterization methodologies including voltage/temperature/frequency and process variation.

Skills

Strategic leadership

Debugging

Validation methodologies

Strong communication

Job description

Altera is seeking an accomplished Memory Validation Architect to define and lead the validation architecture for DDR5, LPDDR5/LPDDR6, HBM, and future memory technologies across our FPGA portfolio. This high-visibility role collaborates with architecture, RTL, firmware, board design, and memory vendors to ensure industry-leading quality and interoperability.

You will mentor engineers, establish scalable validation methodologies, and drive validation from pre-silicon through production, focusing