FPGA DDR and IO Subsystem Architect

191 Altera Corporation; San Jose (CA); On-site; USD 200,400 - 286,000; Full time

Job summary

191 Altera Corporation is looking for a leading architect in High-Speed External Memory systems to develop innovative solutions. The role requires extensive experience in RTL design, memory technologies, and cross-functional collaboration.

The ideal candidate will possess a minimum of a Bachelor's Degree in Electrical Engineering and 10+ years of relevant experience. This position is based in San Jose, California and offers a competitive salary range of $200,400 – $286,000, along with performance-based incentives.

Qualifications

• 10+ years of hands-on experience in RTL design and ASIC design flows.
• Deep understanding of the latest SDRAM technologies.
• Experience architecting and delivering high-speed external memory subsystems.

Responsibilities

• Develop the architecture for High-Speed External Memory.
• Drive architectural trade-off analysis across performance, power, area.
• Engage with customers to understand requirements.

Skills

Verilog

SystemVerilog

C++

Python

DDR4/DDR5

LPDDR4/LPDDR5

Education

Bachelor’s Degree in Electrical Engineering

Master’s or Ph.D. in Electrical Engineering

Job description

Altera is a leading innovator in FPGA technology, delivering programmable solutions that power the world’s data‑centric applications—from cloud and communications infrastructure to automotive, industrial, and edge AI. Our mission is to enable customers to accelerate innovation through high‑performance, power‑efficient, and easy‑to‑use FPGA platforms.

Responsibilities

• Develop the architecture for Altera’s High‑Speed External Memory Interfacing and General‑IO Silicon Subsystem.
• Apply deep knowledge of memory and non‑memory IO applications such as DDR5, LPDDR5, MIPI, LVDS, ONFI, and the competitive landscape to architect Altera’s next‑generation solutions.
• Define subsystem‑level specifications and detailed micro‑architecture in collaboration with circuit design, PHY, controller, packaging, signal integrity, and system teams.
• Own the solution lifecycle from early concept and feasibility analysis through silicon bring‑up, validation, qualification, and production release.
• Partner closely with the Altera Quartus software team to ensure best‑in‑class customer usability, performance tuning, configuration, and debug capabilities.
• Drive architectural trade‑off analysis across performance, power, area (PPA), cost, scalability, and reliability.
• Lead technical reviews and provide guidance across RTL design, circuit design, verification, validation, packaging, and software teams to ensure architectural intent is realized in silicon.
• Analyze competitive FPGA and ASIC IO/memory subsystem implementations to identify differentiation opportunities.
• Engage with strategic customers and ecosystem partners to understand emerging requirements and influence future product roadmaps.

Minimum Qualifications

• Bachelor’s Degree (BE) or higher in Electrical Engineering.
• 10+ years of hands‑on experience in RTL design and ASIC design flows, including synthesis and static timing analysis (STA).
• Strong working knowledge of Verilog, SystemVerilog, C++, and Python.
• Deep understanding of the latest SDRAM technologies with hands‑on experience in DDR4/DDR5 and/or LPDDR4/LPDDR5 controller, PHY, and subsystem design.
• Experience architecting and delivering high‑speed external memory subsystems in advanced semiconductor process nodes.
• Experience in silicon architecture definition, micro‑architecture development, and system‑level trade‑off analysis.
• Experience driving cross‑functional collaboration across RTL design, circuit design, verification, validation, packaging, and software teams.
• Experience in signal integrity, power integrity, timing closure, and high‑speed interface validation methodologies.

Preferred Qualifications

• Master’s or Ph.D. in Electrical Engineering or related discipline.
• Experience with FPGA architectures and programmable IO subsystems.
• Prior ownership of memory controller + PHY co‑architecture and integration.
• Experience collaborating with EDA/software teams to optimize tool flows, configuration, calibration, and debug.
• Familiarity with advanced packaging technologies and multi‑die integration.
• Experience supporting silicon bring‑up, lab characterization, and customer debug.
• Strong communication and technical leadership skills with the ability to influence roadmap decisions.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job‑related knowledge, skills, experiences, trainings, etc. $200,400 – $286,000 USD. We also offer incentive opportunities that reward employees based on individual and company performance.

Job Type & Locations

Job Type: Regular. Shift: Shift 1 (United States of America). Primary Location: San Jose, California, United States. Additional Locations: Posting Statement.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.