Senior FPGA/ASIC Design Engineer (Radar DSP)

Lockheed Martin Corporation; Liverpool Township (OH); On-site; USD 98,000 - 182,000; Full time

Benefits offered by this job

Medical

Dental

Vision

401(k) match

Paid time off

Holidays

Parental Leave

EAP

Flexible Spending Accounts

Life Insurance

Short-Term Disability

Long-Term Disability

Flexible work arrangements

Job summary

Lockheed Martin is seeking an FPGA Engineer to design, verify, and document ASIC/FPGA development. You will work on complex firmware architecture, DSP, high-speed communications, and radar-related algorithms, collaborating with program leadership and peers to break down tasks and guide junior engineers.

The role requires a Bachelor’s degree in EE/CS or related field and 7+ years of experience, with hands-on FPGA experience using Xilinx/AMD and Intel devices, and proficiency in HDL design and DSP

Qualifications

• Bachelor’s degree in Computer Science, Electrical and Computer Engineering or equivalent engineering/technical bachelors degree.
• 7+ years of relevant work experience.
• FPGA architecture and design with applied knowledge of AMD (Xilinx) and/or Altera FPGA devices.

Responsibilities

• Perform complex FPGA firmware architecture and/or custom digital board designs.
• Design digital signal processing, messaging, control, and high-speed communications.
• Interface and collaborate with program leadership and teammates on a regular basis.
• Estimate, break down and plan work for their firmware team.
• Take a high DSP algorithm for a radar system and break it into small pieces and coach junior engineers.

Skills

FPGA design

DSP knowledge

HDL design

System simulation

Leadership

Education

Bachelor’s degree in Computer Science, Electrical/Computer Engineering or equivalent

Tools

Xilinx/Vivado

Intel Quartus

Mentor Questa HDL

System Generator

MATLAB

CUDA/OpenCL

Job description

Lockheed Martin is seeking an FPGA Engineer to design, verify, and document ASIC/FPGA development. You will work on complex firmware architecture, DSP, high-speed communications, and radar-related algorithms, collaborating with program leadership and peers to break down tasks and guide junior engineers.

The role requires a Bachelor’s degree in EE/CS or related field and 7+ years of experience, with hands-on FPGA experience using Xilinx/AMD and Intel devices, and proficiency in HDL design and DSP