Digital Hardware Design Engineer II — FPGA/ASIC

Raytheon

El Segundo (CA)

On-site

USD 76,000 - 144,000

Full time

13 days ago
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Benefits offered by this job

Relocation Eligibility

Job summary

Raytheon seeks a highly skilled Digital Hardware Design Engineer to join our hardware engineering team in El Segundo. You will contribute to the design, verification, and bring-up of airborne radar hardware for defense applications, collaborating with senior engineers on RTL development and FPGA/ASIC workflows.

This role focuses on digital logic design, VHDL/Verilog/SystemVerilog, and hands-on lab work. Candidates should have a strong academic foundation in DSP, timing analysis, and HDL

Qualifications

  • Master's degree in Electrical or Computer Engineering or related STEM field by start date.
  • Strong understanding of digital logic design, RTL/HDL languages, and timing analysis.

Responsibilities

  • Design and implement digital hardware blocks using Verilog/SystemVerilog or VHDL.
  • Develop RTL for FPGA and/or ASIC-based systems.
  • Participate in architecture discussions and design reviews.
  • Create and run simulation testbenches for functional verification.
  • Debug RTL, simulation, synthesis, and hardware integration issues.
  • Collaborate with verification, physical design, firmware, and system teams.

Skills

Digital logic design
RTL design
Verilog/SystemVerilog
VHDL
FPGA/ASIC
Simulation
Timing analysis
Debugging tools
Python
C/C++

Education

Master's degree in EE/CE

Tools

Xilinx Vivado
Intel Quartus
ModelSim/Questa
MATLAB/Simulink

Job description

Raytheon seeks a highly skilled Digital Hardware Design Engineer to join our hardware engineering team in El Segundo. You will contribute to the design, verification, and bring-up of airborne radar hardware for defense applications, collaborating with senior engineers on RTL development and FPGA/ASIC workflows.

This role focuses on digital logic design, VHDL/Verilog/SystemVerilog, and hands-on lab work. Candidates should have a strong academic foundation in DSP, timing analysis, and HDL

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