Space-Grade FPGA Engineer for SDR & DSP

Kepler Communications Inc.; Oregon; Hybrid; USD 96,000 - 165,000; Full time

Benefits offered by this job

Competitive equity plan

Health, dental, and vision insurance

Unlimited vacation and parental leave

Relocation packages

Professional development fund

Company-wide events

Great Place to Work certification

Job summary

Kepler Communications seeks an FPGA Digital Design Engineer for a 6+ month contract to advance our satellite payloads. You will design and implement FPGA code focused on DSP algorithms for onboard SDR systems or embedded interfaces, participating in the full FPGA design flow from simulation to hardware testing.

The role requires a strong background in FPGA/RTL design, Xilinx devices, timing closure, and scripting.

Qualifications

• Bachelor’s Degree required in Computer or Electrical Engineering or equivalent.
• 5+ years of FPGA/RTL design experience.
• Proficiency in Verilog, SystemVerilog, or VHDL with openness to SystemVerilog.
• Experience with Xilinx FPGAs, including Zynq and UltraScale.
• Strong understanding of timing principles, clock domain crossing and timing closure.
• Strong scripting skills (e.g., Python, Tcl, shell).
• Experience with FPGA tools (Vivado, Quartus) and HDL simulators (ModelSim).

Responsibilities

• Develop custom IP for new features of the satellite payloads.
• Iterate DSP and interface designs to improve reliability.
• Collaborate with IP core vendors to integrate functionality.
• Contribute to communications and network architecture planning.
• Participate in conceptual design studies for new spacecraft.

Skills

FPGA design

Verilog

SystemVerilog

VHDL

Xilinx FPGAs

Timing closure

Scripting

Vivado

Quartus

ModelSim

Education

Bachelor's Degree in Computer/Electrical Engineering or equivalent

Master's degree (bonus)

Tools

Vivado

Quartus

ModelSim

Job description

Kepler Communications seeks an FPGA Digital Design Engineer for a 6+ month contract to advance our satellite payloads. You will design and implement FPGA code focused on DSP algorithms for onboard SDR systems or embedded interfaces, participating in the full FPGA design flow from simulation to hardware testing.

The role requires a strong background in FPGA/RTL design, Xilinx devices, timing closure, and scripting.