Senior FPGA Architect for MEMS Timing & Validation

SiTime Corp.; Santa Clara (CA); On-site; USD 148,000 - 204,000; Full time

Benefits offered by this job

401k plan

Health insurance

Parental leave

Paid time off

Job summary

SiTime Corp. in Santa Clara, CA seeks a seasoned FPGA Architect with 10+ years of hands-on FPGA experience to lead the design and development of FPGA-based platforms for MEMS timing product testing.

You will own architecture, RTL design, simulation, timing closure, and bring-up, while mentoring junior engineers. Responsibilities include scalable FPGA solutions, cross-functional collaboration with CMOS, MEMS, systems, and test teams, and driving system-level requirements across hardware,

Qualifications

• 10+ years of hands-on experience in FPGA architecture and development
• Proven track record in designing systems with low jitter and high signal fidelity
• Deep expertise in Verilog/VHDL, simulation tools, and scripting
• Strong understanding of timing analysis and high-speed interfaces (PCIe, DDR, SERDES)

Responsibilities

• Architect and implement scalable FPGA solutions for internal hardware platforms used in MEMS timing product testing
• Lead cross-functional technical initiatives involving CMOS design, MEMS design, systems and test engineering, validation, and production teams
• Define and drive system-level requirements, ensuring alignment across hardware, software, and test domains
• Own the full FPGA lifecycle: architecture, RTL design, simulation, synthesis, timing closure, and bring-up
• Develop reusable IP blocks and maintain a modular, maintainable FPGA infrastructure
• Champion design reviews, documentation standards, and continuous improvement practices
• Provide technical leadership and mentorship to junior engineers and influence strategic direction across multiple programs
• Act as a key technical liaison between engineering, product, and operations teams to ensure seamless integration and execution

Skills

FPGA architecture

Verilog/VHDL

ModelSim/Vivado

Python/TCL scripting

PCIe/DDR/SERDES

Lab bring-up

Leadership

Communication

Education

MS in EE / CE or related

Tools

ModelSim

Vivado

Python

TCL

Logic analyzers

Oscilloscopes

Job description

SiTime Corp. in Santa Clara, CA seeks a seasoned FPGA Architect with 10+ years of hands-on FPGA experience to lead the design and development of FPGA-based platforms for MEMS timing product testing.

You will own architecture, RTL design, simulation, timing closure, and bring-up, while mentoring junior engineers. Responsibilities include scalable FPGA solutions, cross-functional collaboration with CMOS, MEMS, systems, and test teams, and driving system-level requirements across hardware,