Senior FPGA Architect — Precision Timing & MEMS Systems

SiTime Corp.; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

SiTime Corp. in Santa Clara, CA is seeking a seasoned FPGA Architect with 10+ years of experience to lead the design and development of FPGA-based platforms that support internal testing and validation of our precision, high-performance MEMS timing products.

This role is critical to developing robust infrastructure for frequency measurement, low phase noise and low jitter characterization, production, and system-level validation.

Qualifications

• MS in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of hands-on experience in FPGA architecture and development (Xilinx, Intel/Altera, or similar).
• Deep expertise in Verilog/VHDL, simulation tools (ModelSim, Vivado, etc.), and scripting (Python, TCL).
• Proven track record in designing systems with low jitter, low phase noise, and high signal fidelity.
• Strong understanding of timing analysis, clock domain crossing, and high-speed interfaces (PCIe, DDR, SERDES).
• Experience with lab bring-up, debugging tools, and test automation.
• Demonstrated leadership in driving cross-functional initiatives and delivering complex programs.

Responsibilities

• Architect and implement scalable FPGA solutions for internal hardware platforms used in MEMS timing product testing.
• Lead cross-functional technical initiatives involving CMOS design, MEMS design, systems and test engineering, validation, and production teams.
• Define and drive system-level requirements, ensuring alignment across hardware, software, and test domains.
• Own the full FPGA lifecycle: architecture, RTL design, simulation, synthesis, timing closure, and bring-up.
• Develop reusable IP blocks and maintain a modular, maintainable FPGA infrastructure.
• Champion design reviews, documentation standards, and continuous improvement practices.
• Provide technical leadership and mentorship to junior engineers and influence strategic direction across multiple programs.
• Act as a key technical liaison between engineering, product, and operations teams to ensure seamless integration and execution.

Skills

FPGA architecture

Verilog/VHDL

ModelSim

Vivado

Python

TCL

PCIe interface

DDR SERDES

Education

MS in Electrical Engineering

Tools

Vivado

ModelSim

Lab equipment

Job description

SiTime Corp. in Santa Clara, CA is seeking a seasoned FPGA Architect with 10+ years of experience to lead the design and development of FPGA-based platforms that support internal testing and validation of our precision, high-performance MEMS timing products.

This role is critical to developing robust infrastructure for frequency measurement, low phase noise and low jitter characterization, production, and system-level validation.