A leading AI infrastructure company in San Jose seeks a Distinguished Engineer for Formal Verification. This role focuses on defining methodologies for cutting-edge connectivity solutions, including PCIe and CXL. Candidates should have substantial experience in formal verification and a strong background in SystemVerilog. The position offers significant impact on AI infrastructure, requiring advanced scripting knowledge and collaborative skills. Join a dynamic team at the forefront of innovation, with a competitive salary range of $230,000 to $285,000.
Qualifications
15+ years of experience in formal verification or 18+ years in traditional design verification.
Strong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verification.
Advanced scripting abilities with Python or Perl for automation.
Responsibilities
Define and evolve formal verification strategy and methodologies across product lines.
Develop formal verification test plans and collaborate with design teams.
Mentor engineers and develop formal verification models and assertions.
Skills
SystemVerilog
Verilog
Python
Perl
Formal verification techniques
Cross-functional collaboration
Education
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science
Master’s or PhD in relevant fields (preferred)
Tools
Synopsys VCFormal
Cadence JasperGold
Job description
A leading AI infrastructure company in San Jose seeks a Distinguished Engineer for Formal Verification. This role focuses on defining methodologies for cutting-edge connectivity solutions, including PCIe and CXL. Candidates should have substantial experience in formal verification and a strong background in SystemVerilog. The position offers significant impact on AI infrastructure, requiring advanced scripting knowledge and collaborative skills. Join a dynamic team at the forefront of innovation, with a competitive salary range of $230,000 to $285,000.