Senior Firmware Engineer DDR5 PHY & Bare-Metal MCU

Cadence Design Systems, Inc.; Austin (TX); On-site; USD 110,000 - 160,000; Full time

Job summary

Cadence Design Systems, Inc. in Austin is seeking engineers to join the DDR PHY IP Front End Design team. You will develop firmware for DDR5 PHY using microcontrollers and create low-level APIs for embedded systems.

You will collaborate with hardware designers and memory subsystem architects to derive training algorithms and implement them, and work with verification to plan firmware-hardware co-verification. You will also develop and debug on silicon bring-up boards.

Qualifications

• Develop firmware for DDR5 PHY using microcontrollers.
• Bare-metal firmware for high-speed SerDes or memory interface PHY blocks.
• C programming for embedded software development with relevant IDE.
• Debug RTL simulations involving firmware and microcontroller subsystems.
• Collaborate with hardware designers and memory subsystem architects for training algorithms.
• Collaborate with verification team for firmware-hardware co-verification plan.
• Develop and debug on silicon bring-up boards.

Responsibilities

• Develop firmware for DDR5 PHY using microcontrollers.
• Develop low-level APIs for microcontrollers in bare-metal environments.
• Collaborate with hardware designers on training algorithms and PHY performance.
• Coordinate with verification team for firmware-hardware co-verification planning.
• Develop and debug firmware in RTL-based simulations and silicon bring-up tests.

Skills

DDR5 knowledge

Bare-metal firmware

C programming

RTL/Verilog debugging

Scripting (Shell/Perl/Python/TCL)

Verification EDA tools

Education

Bachelor's degree in Electrical Engineering or Computer Science

Tools

Verilog simulators

Waveform viewers

Job description

Cadence Design Systems, Inc. in Austin is seeking engineers to join the DDR PHY IP Front End Design team. You will develop firmware for DDR5 PHY using microcontrollers and create low-level APIs for embedded systems.

You will collaborate with hardware designers and memory subsystem architects to derive training algorithms and implement them, and work with verification to plan firmware-hardware co-verification. You will also develop and debug on silicon bring-up boards.