Principal Firmware Engineer

Cadence Design Systems, Inc.

Austin (TX)

On-site

USD 110,000 - 160,000

Full time

14 days+
Application generator

Stand out for this role — generate a tailored resume and cover letter in about a minute.

Get past ATS filters

Job summary

Cadence Design Systems, Inc. in Austin is seeking engineers to join the DDR PHY IP Front End Design team. You will develop firmware for DDR5 PHY using microcontrollers and create low-level APIs for embedded systems.

You will collaborate with hardware designers and memory subsystem architects to derive training algorithms and implement them, and work with verification to plan firmware-hardware co-verification. You will also develop and debug on silicon bring-up boards.

Qualifications

  • Develop firmware for DDR5 PHY using microcontrollers.
  • Bare-metal firmware for high-speed SerDes or memory interface PHY blocks.
  • C programming for embedded software development with relevant IDE.
  • Debug RTL simulations involving firmware and microcontroller subsystems.
  • Collaborate with hardware designers and memory subsystem architects for training algorithms.
  • Collaborate with verification team for firmware-hardware co-verification plan.
  • Develop and debug on silicon bring-up boards.

Responsibilities

  • Develop firmware for DDR5 PHY using microcontrollers.
  • Develop low-level APIs for microcontrollers in bare-metal environments.
  • Collaborate with hardware designers on training algorithms and PHY performance.
  • Coordinate with verification team for firmware-hardware co-verification planning.
  • Develop and debug firmware in RTL-based simulations and silicon bring-up tests.

Skills

DDR5 knowledge
Bare-metal firmware
C programming
RTL/Verilog debugging
Scripting (Shell/Perl/Python/TCL)
Verification EDA tools

Education

Bachelor's degree in Electrical Engineering or Computer Science

Tools

Verilog simulators
Waveform viewers

Job description

AUSTIN

Full time

R53293

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Be part of the Cadence DDR PHY IP Front End Design team responsible for -

  • Develop firmware for DDR5 PHY using microcontrollers
  • Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers.
  • Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.
  • Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.
  • Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations)
  • Develop and Debug on Silicon bring-up boards.
Required Skills:
  • Good Knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications.
  • Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks.
  • Good Knowledge of C programming language for embedded software development and use of relevant IDE.
  • Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.
  • Good knowledge of Shell/Perl/Python/TCL scripting
  • Good experience on Verification EDA Tools like simulators and waveform viewers

We’re doing work that matters. Help us solve what others can’t.

Equal Employment Opportunity Policy:
  • Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/equal-employment-opportunity-policy.pdf)

We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com.

Privacy Policy:

Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en_US/home/privacy/privacy-policy.html) .

E-Verify Cadence participates in the

E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/e-verify-participation-poster.pdf)

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Principal Firmware Engineer
Principal Firmware Engineer

Cadence Design Systems • Austin (TX)

On-site
USD 110,000 - 170,000
Principal Design Engineer
Principal Design Engineer

Cadence Design Systems • Austin (TX)

On-site
USD 140,000 - 190,000
Principal EDA Software Engineer (C++, Characterization)
Principal EDA Software Engineer (C++, Characterization)

Cadence Design Systems, Inc. • San Jose (CA)

On-site
USD 137,000 - 254,000
Paid vacation and holidays
401(k) plan with employer match
Employee stock purchase plan
Firmware Engineer II
Firmware Engineer II

Cadence • Austin (TX)

On-site
USD 110,000 - 150,000
Lead Design Engineer
Lead Design Engineer

Cadence Design Systems • Cary (NC)

On-site
USD 120,000 - 180,000
Chip Lead / Physical Design Director
Chip Lead / Physical Design Director

Cadence Design Systems, Inc. • Austin (TX)

On-site
USD 180,000 - 260,000
Sr. Principal Software Engineer
Sr. Principal Software Engineer

Cadence Design Systems • Austin (TX)

On-site
USD 196,000 - 364,000
Paid vacation
401(k) plan
Employee stock purchase plan
+2
Design Engineer II
Design Engineer II

Cadence Design Systems • Austin (TX)

On-site
USD 110,000 - 150,000
Senior Principal Design Engineer-Palladium & Protium Customer Enablement & Solutions
Senior Principal Design Engineer-Palladium & Protium Customer Enablement & Solutions

Cadence Design Systems • San Jose (CA)

On-site
USD 154,000 - 286,000
Paid vacation
401(k) plan with employer match
Employee stock purchase plan
+1
Customer Engagement Architect
Customer Engagement Architect

Cadence Design Systems • San Jose (CA)

On-site
USD 186,000 - 345,000
Paid vacation & holidays
401(k) plan with employer match
Employee stock purchase plan
+1