Senior Emulation Engineer: System Bring-Up & Validation

Axiado; Palo Alto (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Axiado seeks a Senior Emulation Engineer to lead system-level validation on ZeBu-based platforms for trusted compute and security features. You will validate firmware, OS, and use-case scenarios, while integrating transactors and ensuring robust hardware-software interoperability.

The role requires deep experience with emulation, SOC design, and R&D collaboration across RTL, DV and SW teams to pre-empt silicon issues and accelerate platform readiness.

Qualifications

• BS or MS in EE/CE or related field required.
• 7+ years hands-on prototyping, emulation, SOC design and validation.
• Experience running and debugging designs on ZeBu or comparable emulators.
• Experience with high/low-speed interfaces and bootloader/kernel bring‑up.
• Scripting in Python, Perl, TCL for automation.
• Strong problem solving, communication and collaboration skills.

Responsibilities

• Execute and debug system-level tests on ZeBu emulation platforms and ensure interfaces are live.
• Bring up secure boot flows and platform security features (root of trust, attestation).
• Develop and run use-case scenarios for platform security and ransomware workloads.
• Triaging failures across RTL, firmware, driver, testbench and emulation environment; produce reproducible bug reports.
• Configure and integrate transactors and speed adapters (PCIe, CXL, Ethernet, NVMe, DDR).
• Develop host utilities and drivers to control XTORs (C/C++, Python, SystemVerilog DPI).
• Collaborate with RTL, DV and SW teams to resolve system-level bugs.

Skills

Problem solving

Communication

Self-driven

Education

B.S./M.S. in EE/CE or related

Tools

ZeBu

Palladium

Veloce

Python

Perl

TCL

SystemVerilog DPI

Job description

Axiado seeks a Senior Emulation Engineer to lead system-level validation on ZeBu-based platforms for trusted compute and security features. You will validate firmware, OS, and use-case scenarios, while integrating transactors and ensuring robust hardware-software interoperability.

The role requires deep experience with emulation, SOC design, and R&D collaboration across RTL, DV and SW teams to pre-empt silicon issues and accelerate platform readiness.