Emulation Engineer (ZeBu Preferred) Location: Sunnyvale, CA

Cystems Logic; Sunnyvale (CA); On-site; USD 90,000 - 120,000; Full time

Job summary

Cystems Logic in Sunnyvale, CA is seeking an experienced Emulation Engineer (ZeBu preferred) to design, implement and optimize hardware emulation environments for complex SoC designs.

You will work with RTL, verification, architecture and software teams to enable pre-silicon validation, accelerate co-verification, and improve emulation throughput. Proficiency with Synopsys ZeBu and RTL/FPGA experience required.

Qualifications

• Must have strong experience in hardware emulation and SoC verification.
• Solid understanding of RTL concepts, Verilog/SystemVerilog.
• Experience with RTL synthesis and emulation implementation flows.

Responsibilities

• Develop, implement, and maintain emulation environments for complex SoCs.
• Work on Synopsys ZeBu platforms for design bring-up and verification.
• Prepare RTL designs for emulation, including synthesis and mapping.

Skills

Hardware emulation

SoC verification

RTL Verilog

Synthesis flows

FPGA-based prototyping

Scripting (Python/Perl/Shell)

Team collaboration

Job description

Company Description

Hi,

Job Title: Emulation Engineer (ZeBu Preferred)

Location: Sunnyvale, CA

Duration: Long Term contract

Preferred Skill: Synopsys ZeBu Emulation Platform

Job Summary

We are looking for an experienced Emulation Engineer with strong expertise in hardware emulation, SoC verification, and FPGA-based prototyping. The ideal candidate should have hands-on experience with hardware emulation platforms, preferably Synopsys ZeBu, and should be capable of developing, deploying, debugging, and optimizing emulation environments for complex SoC designs.

The candidate will work closely with RTL design, design verification, architecture, and software teams to enable pre-silicon validation and accelerate hardware/software co-verification.

Key Responsibilities

• Develop, implement, and maintain hardware emulation environments for complex SoC designs.
• Work on Synopsys ZeBu emulation platforms for design bring-up and verification.
• Prepare RTL designs for emulation, including synthesis, partitioning, mapping, and compilation.
• Debug emulation compilation and runtime issues.
• Develop and integrate testbench components for hardware emulation.
• Support hardware/software co-verification and early software bring-up.
• Optimize emulation performance and improve simulation throughput.
• Work closely with RTL and verification teams to resolve design and emulation issues.
• Integrate processor models, memory models, and peripheral interfaces into emulation environments.
• Support debugging of complex SoC designs using waveforms, logs, and trace analysis.
• Develop scripts and automation for emulation flows.
• Support regression execution and verification sign-off activities.

Required Skills

• Strong experience in hardware emulation and SoC verification.
• Good understanding of digital design concepts and RTL (Verilog/SystemVerilog).
• Experience with RTL synthesis and emulation implementation flows.
• Knowledge of FPGA-based prototyping and hardware acceleration.
• Experience with emulation debugging and performance optimization.
• Understanding of SoC architecture, buses, interfaces, and IP integration.
• Experience with scripting languages such as Python, Perl, or Shell.
• Ability to collaborate with RTL design, verification, and software teams.

All your information will be kept confidential according to EEO guidelines.