Senior EDA Tools & Hardware Engineer (Hybrid)

Intel Corporation; Folsom (CA); Hybrid; USD 142,000 - 269,000; Full time

Job summary

Intel Corporation in Santa Clara, CA seeks a Senior EDA Tools Hardware Engineer to develop transistor‑level timing characterization flows for custom IPs, embedded memories, SRAMs, and macros across advanced nodes. You will own automation and model validation for silicon‑accurate timing, power, and noise modeling.

This role requires expertise in SPICE‑based characterization, Liberty models, and large‑scale automation using Synopsys NanoTime and Cadence Liberate, collaborating with circuit, memory

Qualifications

• Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or related field with 6+ years of relevant experience.
• Master’s degree with 4+ years of relevant experience.
• Ph.D. with 2+ years of relevant experience.
• 3+ years of experience with Timing characterization methodologies (Nanotime, Liberate, PrimeLib).
• Experience with Liberty timing models.

Responsibilities

• Develop, test, and analyze EDA tools, flows, and methodologies to improve efficiency and optimize power and performance.
• Collaborate with EDA vendors to test next‑gen design tools and flows.
• Create and verify hardware designs, integrating components into hierarchical systems for end‑to‑end tool testing.
• Define methodologies for hardware development related to EDA tools and technology node advancements.
• Support and enhance platforms, databases, scripts, and tools used for design automation.
• Provide digital design, verification, full‑chip integration, physical layout, power, performance, clocking, and timing for future TFM development.

Skills

Timing characterization

Liberty timing models

SPICE simulation

Scripting and automation

Education

Bachelor’s degree in Computer Engineering / Electrical Engineering / Computer Science or related field

Master’s degree in Computer Engineering / Electrical Engineering / Computer Science or related field

Ph.D. in Computer Engineering / Electrical Engineering / Computer Science or related field

Tools

Liberate

NanoTime

Job description

Intel Corporation in Santa Clara, CA seeks a Senior EDA Tools Hardware Engineer to develop transistor‑level timing characterization flows for custom IPs, embedded memories, SRAMs, and macros across advanced nodes. You will own automation and model validation for silicon‑accurate timing, power, and noise modeling.

This role requires expertise in SPICE‑based characterization, Liberty models, and large‑scale automation using Synopsys NanoTime and Cadence Liberate, collaborating with circuit, memory