Senior EDA Tools Hardware Engineer

Intel Corporation; Hillsboro (OR); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plans

Paid vacation

Job summary

Intel Corporation in US (Santa Clara/Folsom/Hillsboro) seeks a Senior EDA Tools Hardware Engineer to develop transistor-level timing characterization flows for custom IPs and macros across advanced silicon technologies.

The role emphasizes SPICE-based characterization, Liberty model generation, and large-scale automation using Synopsys NanoTime and Cadence Liberate. Hybrid work model offered in multiple US locations.

Qualifications

• Degree in Computer/Electrical Engineering or Computer Science with related experience.
• 3+ years of timing characterization experience with Nanotime, Liberate, or PrimeLib.
• Experience with Liberty timing models.

Responsibilities

• Develop and optimize EDA tool flows for timing, power, and area.
• Collaborate with EDA vendors to evaluate new tools and flows.
• Create and verify hardware designs integrated into hierarchical systems for tool testing.
• Define methodologies for hardware development related to EDA tools and nodes.
• Support tools, databases, scripts, and platforms used in design automation.
• Provide timing, power, and clocking insights for future TFM development.

Skills

EDA CAD

Timing characterization

Scripting & automation

Linux environments

Vendor collaboration

Education

Bachelor’s/Master’s/ PhD in relevant field

6+ years experience (Bachelor)

4+ years experience (Master)

Tools

NanoTime

Liberate

PrimeLib

Liberty models

Job description

The Role and Impact

Join Intel's mission to engineer world-changing technology as a Senior EDA Tools Hardware Engineer. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files, and compiler-generated macros across advanced semiconductor technologies.

Job Details

Job Description: This role focuses on characterization methodology, CAD infrastructure, automation, and model validation for complex custom macros and memory IPs. The engineer will work closely with custom circuit, memory design, STA, and methodology teams to enable scalable and silicon-accurate timing, power, and noise modeling flows. The ideal candidate has strong expertise in SPICE-based characterization, Liberty model generation, custom macro timing behavior, and large-scale automation using industry-standard tools such as Synopsys NanoTime and Cadence Liberate.

Key Responsibilities

• Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance.
• Collaborate with EDA vendors to define, evaluate, and test next-generation design tools and flows.
• Create and verify unique hardware designs, integrating components into hierarchical systems to support end-to-end EDA tool testing for advanced technology nodes.
• Define and enable methodologies for hardware development related to EDA tools and technology node advancements.
• Support and enhance platforms, databases, scripts, and tools used for design automation.
• Provide digital design, verification, full-chip integration, physical layout, power, performance, clocking, and timing for future TFM development.

Qualifications

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Degree in one of the following options:
  • Option 1: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field, with 6+ years of relevant experience.
  • Option 2: Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 4+ years of relevant experience.
  • Option 3: Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 2+ years of relevant experience.
• 3+ years of experience with Timing characterization methodologies in one of the following: (i.e. Nanotime, Liberate, or PrimeLib).
• Experience with Liberty timing models.

Preferred Qualifications

• Experience in any of the following:
  • SPICE simulation
  • CMOS circuits
  • Memory architecture fundamentals
  • STA fundamentals
  • Advanced-node custom IP or memory characterization flows
  • Scripting and automation skills in Linux environments

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, California, Santa Clara

Additional Locations

US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.