Senior EDA Tools Engineer — Timing, ML & Performance

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 137,000 - 254,000; Full time

Benefits offered by this job

Paid vacation and holidays

401(k) plan with employer match

Employee stock purchase plan

Job summary

Cadence Design Systems, Inc. is seeking a seasoned software engineer to advance our transistor‑level timing, power, and reliability analysis tools.

You will design new architectures and extend frameworks to handle complex timing challenges in modern chips. With 8+ years in EDA tool development and expert C++ skills in Linux, you will optimize data structures and algorithms while applying best practices for high‑quality software engineering.

Qualifications

• 8+ years of experience in development of EDA tools and expertise in transistor-level timing, power, noise, aging, reliability, and EMIR analysis.
• Hardcore C++ knowledge, particularly in a Linux environment.
• Strong proficiency in designing data structures, algorithms, and applying software engineering principles.
• Industry experience developing and maintaining C++ based applications on Unix or Linux platforms.

Responsibilities

• Enhance and expand existing tools' architecture to cover timing analysis.
• Create new frameworks for analyzing effects dominant at n5 and below.
• Leverage machine learning technology to achieve significant improvements in speed, capacity, and usability over existing solutions.

Skills

EDA tools

C++

Data structures

Unix/Linux

Education

BS in CS/EE/CE

Tools

Linux

Job description

Cadence Design Systems, Inc. is seeking a seasoned software engineer to advance our transistor‑level timing, power, and reliability analysis tools.

You will design new architectures and extend frameworks to handle complex timing challenges in modern chips. With 8+ years in EDA tool development and expert C++ skills in Linux, you will optimize data structures and algorithms while applying best practices for high‑quality software engineering.