Senior EDA Tools Hardware Engineer - Hybrid + Stock

Intel Corporation; Santa Clara (CA); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Health benefits

Stock bonuses

Retirement plan

Job summary

Intel Corporation in California is seeking a Senior EDA Tools Hardware Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, and macros across advanced technologies. You will drive automation and model validation for silicon-accurate timing, power, and noise modeling flows, collaborating with circuit, memory design, and STA teams.

The role emphasizes SPICE-based characterization, Liberty model generation, and large-scale

Qualifications

• 6+ years of relevant experience in timing characterization methodologies.
• Experience with Liberty timing models and SPICE-based characterization.
• Automation and Linux scripting skills for EDA workflows.

Responsibilities

• Develop, test, and analyze EDA tools, flows, and methodologies.
• Collaborate with EDA vendors to define and test next-generation design tools.
• Create and verify hardware designs for hierarchical systems to support EDA testing.
• Define methodologies for hardware development related to EDA tools and node advancements.
• Support and enhance platforms, databases, scripts, and tools used for design automation.
• Provide timing, power, and clocking analyses for future TFM development.

Skills

Timing characterization

Automation

Hardware design

Education

Bachelor's degree in Computer Engineering/Electrical Engineering/Computer Science

Master's degree in Computer Engineering/Electrical Engineering/Computer Science

Ph.D. in Computer Engineering/Electrical Engineering/Computer Science

Tools

Synopsys NanoTime

Cadence Liberate

PrimeLib

Job description

Intel Corporation in California is seeking a Senior EDA Tools Hardware Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, and macros across advanced technologies. You will drive automation and model validation for silicon-accurate timing, power, and noise modeling flows, collaborating with circuit, memory design, and STA teams.

The role emphasizes SPICE-based characterization, Liberty model generation, and large-scale