Senior EDA Tools Hardware Engineer

Intel Corporation; Santa Clara (CA); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Health benefits

Stock bonuses

Retirement plan

Job summary

Intel Corporation in California is seeking a Senior EDA Tools Hardware Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, and macros across advanced technologies. You will drive automation and model validation for silicon-accurate timing, power, and noise modeling flows, collaborating with circuit, memory design, and STA teams.

The role emphasizes SPICE-based characterization, Liberty model generation, and large-scale

Qualifications

• 6+ years of relevant experience in timing characterization methodologies.
• Experience with Liberty timing models and SPICE-based characterization.
• Automation and Linux scripting skills for EDA workflows.

Responsibilities

• Develop, test, and analyze EDA tools, flows, and methodologies.
• Collaborate with EDA vendors to define and test next-generation design tools.
• Create and verify hardware designs for hierarchical systems to support EDA testing.
• Define methodologies for hardware development related to EDA tools and node advancements.
• Support and enhance platforms, databases, scripts, and tools used for design automation.
• Provide timing, power, and clocking analyses for future TFM development.

Skills

Timing characterization

Automation

Hardware design

Education

Bachelor's degree in Computer Engineering/Electrical Engineering/Computer Science

Master's degree in Computer Engineering/Electrical Engineering/Computer Science

Ph.D. in Computer Engineering/Electrical Engineering/Computer Science

Tools

Synopsys NanoTime

Cadence Liberate

PrimeLib

Job description

Introduction

Job Details: Job Description: The Role and Impact Join Intel's mission to engineer world-changing technology as a Senior EDA Tools Hardware Engineer. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files, and compiler-generated macros across advanced semiconductor technologies. This role focuses on characterization methodology, CAD infrastructure, automation, and model validation for complex custom macros and memory IPs. The engineer will work closely with custom circuit, memory design, STA, and methodology teams to enable scalable and silicon-accurate timing, power, and noise modeling flows. The ideal candidate has strong expertise in SPICE-based characterization, Liberty model generation, custom macro timing behavior, and large-scale automation using industry-standard tools such as Synopsys NanoTime and Cadence Liberate.

Key Responsibilities

• Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance.
• Collaborate with EDA vendors to define, evaluate, and test next-generation design tools and flows.
• Create and verify unique hardware designs, integrating components into hierarchical systems to support end-to-end EDA tool testing for advanced technology nodes.
• Define and enable methodologies for hardware development related to EDA tools and technology node advancements.
• Support and enhance platforms, databases, scripts, and tools used for design automation.
• Provide digital design, verification, full-chip integration, physical layout, power, performance, clocking, and timing for future TFM development.

Minimum Qualifications

• Degree in one of the following options: Option 1: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field, with 6+ years of relevant experience.
• Option 2: Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 4+ years of relevant experience.
• Option 3: Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 2+ years of relevant experience.
• 3+ years of experience with Timing characterization methodologies in one of the following: (i.e. Nanotime, Liberate, or PrimeLib).
• Experience with Liberty timing models.

Preferred Qualifications

• Experience in any of the following: SPICE simulation CMOS circuits.
• Memory architecture fundamentals.
• STA fundamentals.
• Advanced-node custom IP or memory characterization flows.
• Scripting and automation skills in Linux environments.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations: US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

• competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

* Job posting details (such as work model, location or time type) are subject to change.

* ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.