Senior EDA/IC CAD Engineer - FinFET PDK & Flow Automation

Anysilicon; San Jose (CA); Hybrid; USD 150,000 - 210,000; Full time

Job summary

Anysilicon is seeking an experienced IC CAD/Design Methodology Engineer to manage and optimize advanced foundry PDKs for FinFET technologies. You will collaborate with design teams and EDA vendors to enhance methodologies and boost design productivity.

Main duties include qualifying and maintaining PDKs for 2nm/3nm/5nm FinFETs, developing Cadence-based design flows for analog/mixed-signal/RF, and establishing physical verification processes with Calibre/StarRC.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related.
• 5+ years hands-on IC CAD/Design Methodology experience in advanced semiconductor technologies.

Responsibilities

• Manage, qualify, and maintain advanced foundry PDKs for FinFET technologies (2nm/3nm/5nm).
• Develop and support Cadence-based design flows for analog, mixed-signal, RF, and high-speed interface designs.
• Establish physical verification and signoff methodologies using Calibre and StarRC extraction flows.
• Support advanced reliability verification, including EMIR analysis and electrical rule checking.
• Drive flow automation, scripting, and tool integration to enhance design productivity.
• Collaborate with design teams, foundries, and EDA vendors to resolve technical challenges.

Skills

Advanced-node FinFET knowledge

SKILL scripting

Perl scripting

Python scripting

Tcl scripting

Shell scripting

Linux compute clusters

Physical verification

Calibre familiarity

Cadence design tools

Education

Bachelor's or Master's in Electrical/Computer Engineering/CS

Tools

Calibre

StarRC

Cadence Virtuoso

Cadence Innovus

Synopsys tools

Job description

Anysilicon is seeking an experienced IC CAD/Design Methodology Engineer to manage and optimize advanced foundry PDKs for FinFET technologies. You will collaborate with design teams and EDA vendors to enhance methodologies and boost design productivity.

Main duties include qualifying and maintaining PDKs for 2nm/3nm/5nm FinFETs, developing Cadence-based design flows for analog/mixed-signal/RF, and establishing physical verification processes with Calibre/StarRC.