Senior CAD Architect: AI-Driven SoC Flows

Ampere Computing; Santa Clara (CA); On-site; USD 293,000 - 440,000; Full time

Benefits offered by this job

Health insurance

401K retirement plan

Unlimited flextime

Dental and vision

Job summary

Ampere Computing is seeking a Distinguished Engineer to lead CAD flows for high-performance SoC/ASIC designs. You will guide RTL synthesis, placement, CTS, routing, and timing closure, while driving automation, PPA optimization, and tool interoperability across architecture, design, verification, and manufacturing teams.

You will collaborate with RTL, DFT, architecture, and physical implementation groups, integrating PDKs and managing sub-micron physical effects with robust scripting (Tcl,

Qualifications

• 15+ years in semiconductor CAD/EDA development or flow engineering.
• Proven track record leading complex CAD flow projects.
• Deep knowledge of RTL synthesis, placement & routing, timing closure, signoff and manufacturability.
• Expertise with major EDA tools (Synopsys, Cadence, Mentor) and scripting languages (Tcl, Python, Perl).
• Strong problem-solving skills and ability to drive cross-functional collaboration.
• Excellent communication skills and experience mentoring senior engineers.
• Experience with cloud-based design environments and scalable compute infrastructure.
• Electrical or Computer Engineering degree with extensive related experience.

Responsibilities

• Define global physical design methodology across synthesis, floorplanning, placement, CTS, routing, timing, and physical verification.
• Architect and deploy advanced CAD flows for SoC/ASIC designs.
• Explore AI/ML-driven EDA features to optimize PPA and shorten turnaround times.
• Build and drive PPA optimization recipes for subsystems.
• Lead low-power flow enhancements for multi-power domains (UPF).
• Drive innovation in hierarchical design and multi-die/chiplet integration.
• Allocate resources to support multi-project execution timelines.
• Develop a culture of automation and engineering excellence.
• Benchmark and select state-of-the-art EDA tools and scripting infrastructure.

Skills

CAD/EDA leadership

RTL synthesis

Scripting (Tcl/Python/Perl)

Cross-functional collaboration

Education

Bachelor's degree in EE/CE

Tools

Innovus

Fusion Compiler

PrimeTime

Calibre

Job description

Ampere Computing is seeking a Distinguished Engineer to lead CAD flows for high-performance SoC/ASIC designs. You will guide RTL synthesis, placement, CTS, routing, and timing closure, while driving automation, PPA optimization, and tool interoperability across architecture, design, verification, and manufacturing teams.

You will collaborate with RTL, DFT, architecture, and physical implementation groups, integrating PDKs and managing sub-micron physical effects with robust scripting (Tcl,