Staff DV Engineer

E-Space

Saratoga (CA)

On-site

USD 120,000 - 220,000

Full time

14 days+

Get more replies from employers

Send a job-specific resume in minutes.

Benefits offered by this job

Health and wellness care options

Paid holidays

Continuous learning and development

Competitive salaries

Job summary

E-Space in Saratoga is seeking a Digital Design Verification Engineer with over 6 years of experience in the semiconductor industry. The role focuses on verifying custom ASICs for satellite and wireless telephony, with a strong emphasis on Verilog and SystemVerilog. You'll contribute to test planning and execution, ensuring high standards in verification practices. Competitive salaries and benefits are provided, catering to innovative thinkers ready to shape the future of satellite technology.

Qualifications

6+ years of design verification experience in the semiconductor industry.
Strong proficiency in Verilog and SystemVerilog.
Experience writing tests within an existing UVM verification environment.

Responsibilities

Verify custom ASICs for satellite and wireless telephony.
Lead design verification efforts at the block level.
Debug RTL simulations independently.

Skills

Verilog

SystemVerilog

UVM

C/C++

Perl

Python

Job description

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work.

Requirements

HDL & Verification Methodology
Strong proficiency in Verilog and SystemVerilog
Experience writing tests within an existing UVM verification environment
Solid understanding of UVM architecture and methodology

Programming & Scripting

Ability to write C/C++ code for verification purposes
Some scripting experience in Perl or Python

Verification Planning & Execution

Ability to contribute to and help write test plans
Experience writing and maintaining verification tests
Ability to debug RTL simulations independently

Leadership

Experience leading design verification efforts at the block level
Experience driving code coverage closure on assigned blocks

What you bring to this role

6+ years of design verification experience in the semiconductor industry

This is a full time, exempt position, based out of our Saratoga office. The target base pay for this position is $120,000 - $220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience.

We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in‑orbit activities. If that’s your experience – then we’ll be immediately wow‑ed.

E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.

Benefits