Principal DFT Engineer – AI Chip SoC Test (Equity)

SambaNova; Austin (TX); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Health insurance

HSA (Health Savings Account)

Dental & Vision

Job summary

SambaNova is seeking a talented Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for ML/AI. You will be a hands-on engineer responsible for DFT architecture, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips.

Responsibilities include defining block- and SoC-level DFT, developing ATPG flows, automation scripts, and JTAG/IJTAG infrastructure for internal test.

Qualifications

• B.S. in computer science or related field.
• 10+ years relevant industry experience.
• Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG, and hierarchical DFT.
• Hands-on experience with Siemens Tessent tool flow (preferred) or equivalent industry standard DFT tools.
• Familiarity with IEEE 1500, IEEE 1687/IJTAG, and low-power DFT is highly desirable.
• Strong understanding of advanced ATPG, silicon diagnosis, and failure localization methodologies.
• Experience with STA constraints & analysis for DFT modes & SDF simulations.
• Working knowledge of Verilog/System-Verilog simulators & waveform debugging.

Responsibilities

• Define & implement block-level and SoC-level DFT architecture for large, hierarchical SoCs
• Develop and maintain ATPG flows for stuck-at, at-speed and advanced fault models.
• Develop scripts and automation for DFT insertion, ATPG, coverage analysis, pattern generation, and debug.
• Develop and maintain JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure for internal test and debug access.
• Generate production-quality ATPG and MBIST patterns and support deployment to ATE.
• Work closely with STA and Physical Design teams on DFT timing closure
• Support silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization.

Skills

DFT concepts

Verilog/SystemVerilog

STA & timing analysis

Debugging & waveform analysis

IEEE 1500/IJTAG

JTAG & MBIST

Education

B.S. in Computer Science or Computer/Electrical Engineering

Tools

Siemens Tessent

Pattern generation tools

ATE pattern deployment

Job description

SambaNova is seeking a talented Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for ML/AI. You will be a hands-on engineer responsible for DFT architecture, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips.

Responsibilities include defining block- and SoC-level DFT, developing ATPG flows, automation scripts, and JTAG/IJTAG infrastructure for internal test.