Senior DSP & System Validation Engineer (Equity + Bonus)

Broadcom; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program

Employee Assistance Program

company paid holidays

paid sick leave and vacation time

Paid family leave as applicable

Job summary

Broadcom is seeking a Digital Signal Processing and System Validation Engineer to design DSP blocks for next-generation optical data center connectivity products. You will validate the ASIC architecture both pre- and post-silicon, collaborating with RTL and verification teams.

Ideal candidates hold an MS in EE or CE with 10+ years (PhD with 7+ years) of DSP experience in SerDes and high-speed data center networking, and are proficient with Verilog, Matlab/Simulink, and front-end tools.

Qualifications

• MS in Electrical Engineering or Computer Engineering with 10+ years or PhD with 7+ years in DSP design for SerDes and high-speed data center networking.
• Experience in post silicon validation of digital and analog mixed-signal IPs.
• Deep understanding of 100G/200G/400G PAM4 and NRZ architectures and trade-offs.
• Experience translating CDR and equalization architectures into Verilog for synthesis.

Responsibilities

• Design digital signal processing blocks for next-generation optical data center connectivity products.
• Validate ASIC architecture post- and pre-silicon.
• Collaborate with RTL, verification, and design teams to meet timing, power and area goals.

Skills

DSP design

SerDes

FFT/Filter

RTL coding

Verilog/SystemVerilog

Matlab/Simulink

Front-end tools

Timing analysis

Education

MS in EE or CE

PhD in EE or CE

Tools

NCVerilog

NCSIM

Simvision

Spyglass

Job description

Broadcom is seeking a Digital Signal Processing and System Validation Engineer to design DSP blocks for next-generation optical data center connectivity products. You will validate the ASIC architecture both pre- and post-silicon, collaborating with RTL and verification teams.

Ideal candidates hold an MS in EE or CE with 10+ years (PhD with 7+ years) of DSP experience in SerDes and high-speed data center networking, and are proficient with Verilog, Matlab/Simulink, and front-end tools.