Digital Signal Processing and System Validation Engineer

Broadcom; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program

Employee Assistance Program

company paid holidays

paid sick leave and vacation time

Paid family leave as applicable

Job summary

Broadcom is seeking a Digital Signal Processing and System Validation Engineer to design DSP blocks for next-generation optical data center connectivity products. You will validate the ASIC architecture both pre- and post-silicon, collaborating with RTL and verification teams.

Ideal candidates hold an MS in EE or CE with 10+ years (PhD with 7+ years) of DSP experience in SerDes and high-speed data center networking, and are proficient with Verilog, Matlab/Simulink, and front-end tools.

Qualifications

• MS in Electrical Engineering or Computer Engineering with 10+ years or PhD with 7+ years in DSP design for SerDes and high-speed data center networking.
• Experience in post silicon validation of digital and analog mixed-signal IPs.
• Deep understanding of 100G/200G/400G PAM4 and NRZ architectures and trade-offs.
• Experience translating CDR and equalization architectures into Verilog for synthesis.

Responsibilities

• Design digital signal processing blocks for next-generation optical data center connectivity products.
• Validate ASIC architecture post- and pre-silicon.
• Collaborate with RTL, verification, and design teams to meet timing, power and area goals.

Skills

DSP design

SerDes

FFT/Filter

RTL coding

Verilog/SystemVerilog

Matlab/Simulink

Front-end tools

Timing analysis

Education

MS in EE or CE

PhD in EE or CE

Tools

NCVerilog

NCSIM

Simvision

Spyglass

Job description

Job Description: Broadcom is looking for a Digital Signal Processing and System Validation Engineer. In this highly visible role, you will be designing digital signal processing blocks for the next generation of optical data center connectivity products. You will be responsible for validating the ASIC architecture post and pre-silicon.

Qualifications include

• MS in Electrical Engineering or Computer Engineering with 10+ years or PhD with 7+ years of experience in digital signal processing design for SerDes and serial link high-speed data center networking.
• Experience in post silicon validation of digital and analog mixed-signal IPs.
• Deep understanding of ADC and analog based optical and electrical interconnect architectures such as 100G/200G/400G per lane PAM4 and NRZ design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime.
• Experience translating CDR and equalization architectures into Verilog code for logic synthesis.
• Proficient with Matlab, Simulink and Verilog-HDL/System Verilog coding.
• Experience with front end tools such as NCVerilog, NCSIM, Simvision, Spyglass.
• Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL.
• Experience in synthesis, CDC, static timing analysis.
• Exposure to SDF annotated simulations with good understanding of parasitic delays.

Highly Desired Qualifications

• Good understanding of high speed DSP applications and algorithms.
• Prior experience of high speed ADC, FFE, DFE, CDR Adaptation algorithms for PAM4 signals.
• Understanding of logic optimization for low power, timing margins & DFT.
• Deep understanding of Signal Integrity and Power Integrity modeling for High Speed designs.
• Understanding & exposure to Verilog AMS simulation, experience in behavioral models of analog circuits will be helpful.
• Willing to work in a multifunctional role.
• Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels.
• Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results.
• Excellent time and task management, and interpersonal skills.

Compensation And Benefits

The annual base salary range for this position is To

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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